
Master Bus Operation
3-24
ColdFire2/2M User’s Manual
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MOTOROLA
Clock 2 (C2)
During the first half of C2, the ColdFire2/2M negates MTSB. Because the MKILLB signal
was not asserted during the rising clock edge of C2, the selected device uses the MRWB
and MSIZ signals to place the data on the master read data bus (MRDATA[31:0]) and assert
the master input enable (MIE) signal. Concurrently, the selected device asserts the master
transfer acknowledge (MTAB) signal. At the end of C2, the ColdFire2/2M samples the level
of MTAB and captures the current value on MRDATA[31:0]. If MTAB is asserted, the transfer
terminates. If MTAB is not asserted, the ColdFire2/2M ignores the data and inserts wait
states instead of terminating the transfer. The ColdFire2/2M continues to sample MTAB on
successive rising edges of CLK until it is asserted. The selected device negates the MIE and
MTAB signals in the first half of the next CLK cycle.
Clock 3 (C3)
The read cycle starts in C3. The ColdFire2/2M asserts the MTSB signal, and then the
MKILLB signal. This signifies that the M-Bus cycle must be inhibited; i.e. the access has “hit”
in an internal-bus memory.
Clock 4 (C4)
Nop.
Clock 5 (C5)
The read cycle starts in C5. The ColdFire2/2M asserts the MTSB signal, and then the
MKILLB signal. This signifies that the M-Bus cycle must be inhibited; i.e. the access has “hit”
in an internal K-Bus memory.
Clock 6 (C6)
Another read cycle starts in C6. The C1 description applies here.
Clock 7 (C7)
During the first half of C7, the ColdFire2/2M negates MTSB. Because the MKILLB signal
was not asserted during the rising clock edge of C7, the selected device uses the MRWB
and MSIZ signals to place the data on the master read data bus (MRDATA[31:0]). The rest
of the C2 description applies here.
3.6 PIPELINE STALLS
In an idealized environment for maximum performance, all ColdFire2/2M references are
mapped to integrated memory resources and complete in a single clock cycle. Any memory
reference that generates a master bus access stalls the processor pipeline since the internal
transfer cannot be completed in a single clock cycle. This performance degradation factor
can be expressed as:
Pipeline Stall = Master Bus Clock Cycles - 1
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