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參數(shù)資料
| 型號： | COLDFIRE2UM |
| 英文描述： | Version 2/2M ColdFire Core Processor User＇s Manual |
| 中文描述： | 版本2/2M ColdFire內(nèi)核的處理器用戶手冊 |
| 文件頁數(shù)： | 101/253頁 |
| 文件大小： | 1762K |
| 代理商： | COLDFIRE2UM |
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Exception Processing
4-8
ColdFire2/2M User’s Manual
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
in the PC. If an access error or address error occurs before the first instruction begins
execution, the ColdFire2/2M enters the fault-on-fault halted state. Refer to
Reset Operation
for more information on initiating a reset exception.
Section 3.9
4.2.2 Access Error Exception
An access error exception, vector number $2, occurs when a bus cycle terminates with an
error condition such as the assertion of the master transfer error acknowledge (MTEAB)
signal. Refer to
Section 3.8 Master Bus Exception Control Cycles
. The exact response to an
access error is dependent on the type of memory reference being performed.
For an instruction fetch, the ColdFire2/2M postpones the reporting of an error until the
faulted reference is needed by an instruction to be executed. Thus, faults which occur during
instruction prefetches which are then followed by a change of instruction flow will not
generate an exception. When the ColdFire2/2M attempts to execute an instruction with a
faulted opword and/or extension words, the access error will be signaled and the instruction
aborted. For this type of exception, the programming model has not been altered by the
instruction generating the access error.
If the access error occurs on an operand read, the ColdFire2/2M immediately aborts the
current instruction’s execution and initiates exception processing. In this situation, any
address register updates due to the auto-addressing modes, {e.g., (An)+,-(An)}, will already
have been performed. Thus, the programming model contains the updated An value. In
addition, if an access error occurs during the execution of a MOVEM instruction loading
registers from memory, any registers already updated before the fault occurs will contain the
operands from memory.
The ColdFire2/2M uses an imprecise reporting mechanism for access errors on write
operations. Since the actual write cycle may be decoupled from the ColdFire2/2M’s
execution of the instruction requesting the write, the signaling of an access error appears to
be decoupled from the instruction which generated the write. Accordingly, the PC contained
in the exception stack frame merely represents the location in the program when the access
error was signaled, not when the offending instruction was executed. All programming
model updates associated with the write instruction are completed. The NOP instruction can
be used for purposes of collecting access errors for writes. This instruction delays its
execution until all previous operations, including all pending write operations to internal
memory resources, are complete. Noncachable writes to the master bus may be buffered
but will be completed before the execution of a NOP instruction. The NOP instruction waits
until the pipeline is cleared out, including buffered writes before executing. Generally,
buffering can provide higher performance, although issues concerning recovery from
physical write-errors may become more difficult to resolve.
4.2.3 Address Error Exception
Any attempted execution transferring control to an odd instruction address (i.e., if bit 0 of the
target address is set) results in an address error exception, vector number $3. For
conditional branch instructions, the exception is generated regardless of the taken/not-taken
resolution of the branch condition.
F
Freescale Semiconductor, Inc.
n
.
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