MOTOROLA
ColdFire2/2M User’s Manual
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vii
TABLE OF CONTENTS
Paragraph
Number
Page
Number
Title
Section 1
Overview
1.1
1.1.1
1.1.2
1.2
1.3
1.3.1
1.3.1.1
1.3.1.2
1.3.1.3
1.3.1.4
1.3.2
1.3.2.1
1.3.2.2
1.3.2.3
1.3.2.4
1.3.2.5
1.3.2.6
1.3.2.7
1.3.2.8
1.3.2.9
1.4
1.4.1
1.4.1.1
1.4.1.2
1.4.1.3
1.4.1.4
1.4.1.5
1.4.2
1.4.2.1
1.4.2.2
1.4.2.3
1.4.3
FlexCore Integrated Processors..................................................................1-2
FlexCore Advantages.............................................................................1-4
FlexCore Module Types .........................................................................1-4
Development Cycle......................................................................................1-5
System Architecture.....................................................................................1-8
Internal Bus Structure.............................................................................1-8
Master Bus.........................................................................................1-8
Slave Bus...........................................................................................1-9
External Bus ......................................................................................1-9
Test Bus.............................................................................................1-9
System Functional Blocks ......................................................................1-9
Alternate Master ................................................................................1-9
ColdFire2/2M.....................................................................................1-9
I-Cache Data Array..........................................................................1-10
I-Cache Tag Array ...........................................................................1-10
Master Bus Arbiter (MARB) .............................................................1-10
ROM Array.......................................................................................1-11
Slave Modules.................................................................................1-11
SRAM Array.....................................................................................1-11
System Bus Controller (SBC) ..........................................................1-11
Programming Model ..................................................................................1-11
Integer Unit User Programming Model.................................................1-11
Data Registers (D0 – D7) ................................................................1-12
Address Registers (A0 – A6)...........................................................1-12
Stack Pointer (A7,SP)......................................................................1-12
Program Counter (PC).....................................................................1-12
Condition Code Register (CCR) ......................................................1-12
MAC Unit User Programming Model ....................................................1-13
Accumulator (ACC)..........................................................................1-14
Mask Register (MASK) ....................................................................1-14
MAC Status Register (MACSR).......................................................1-14
Supervisor Programming Model...........................................................1-14
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