參數(shù)資料
型號(hào)： COLDFIRE2UM
英文描述： Version 2/2M ColdFire Core Processor User＇s Manual
中文描述： 版本2/2M ColdFire內(nèi)核的處理器用戶手冊(cè)
文件頁(yè)數(shù)： 104/253頁(yè)
文件大?。?/td> 1762K
代理商： COLDFIRE2UM
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Exception Processing
MOTOROLA
ColdFire2/2M User’s Manual
For More Information On This Product,
Go to: www.freescale.com
4-11
4.2.11 Interrupt Exception
When a peripheral device requires the services of the ColdFire2/2M or is ready to send
information that the ColdFire2/2M requires, it can signal the ColdFire2/2M to take an
interrupt exception. Seven levels of interrupt priorities are provided, numbered 1–7. Devices
can be chained externally within interrupt priority levels, allowing an unlimited number of
peripheral devices to interrupt the ColdFire2/2M. The status register contains a 3-bit mask
indicating the current interrupt priority, and interrupts are inhibited for all priority levels less
than or equal to the current priority (see
Section 1.4.3.1 Status Register (SR)
.)
An interrupt request is made to the ColdFire2/2M by encoding the interrupt request levels
1–7 on the three interrupt request level (IPLB[2:0]) signals; all signals high indicate no
interrupt request.
Table 4-4
shows the relationship between the actual requested interrupt
and the state of the IPLB[2:0] signals as well as the interrupt mask levels required for
recognition of the requested level.
Interrupt requests arriving at the ColdFire2/2M do not force immediate exception
processing, but the requests are made pending. Pending interrupts are detected between
instruction executions. If the priority of the pending interrupt is lower than or equal to the
current ColdFire2/2M priority, execution continues with the next instruction, and the
requesting interrupt is postponed until the priority of the pending interrupt becomes greater
than the current ColdFire2/2M priority.
If the priority of the pending interrupt is greater than the current ColdFire2/2M priority, the
exception processing sequence for the requesting interrupt is started. A copy of the status
register is saved internally; the privilege mode is set to supervisor mode; tracing is
suppressed; and the ColdFire2/2M priority level is set to the level of the interrupt being
acknowledged. The ColdFire2/2M fetches the vector number from the interrupting device by
executing an interrupt acknowledge cycle, which displays the level number of the interrupt
being acknowledged on the address bus (see
Section 3.7 Interrupt Acknowledge Bus
Cycles
). The ColdFire2/2M then proceeds with the usual exception processing, saving the
exception stack frame on the supervisor stack. The saved value of the program counter is
the address of the instruction that would have been executed had the interrupt not been
taken. The appropriate interrupt vector is fetched and loaded into the program counter, and
normal instruction execution commences in the interrupt handling routine.
Table 4-4. Interrupt Levels and Mask Values
REQUESTED
INTERRUPT LEVEL
CONTROL LINE STATUS
INTERRUPT MASK LEVEL
REQUIRED FOR RECOGNITION
IPLB[2]
High
High
High
High
Low
Low
Low
Low
IPLB[1]
High
High
Low
Low
High
High
Low
Low
IPLB[0]
High
Low
High
Low
High
Low
High
Low
0
1
2
3
4
5
6
7
No Request
0
0-1
0-2
0-3
0-4
0-5
0-7
F
Freescale Semiconductor, Inc.
n
.
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