參數(shù)資料
型號(hào)： COLDFIRE2UM
英文描述： Version 2/2M ColdFire Core Processor User＇s Manual
中文描述： 版本2/2M ColdFire內(nèi)核的處理器用戶手冊(cè)
文件頁(yè)數(shù)： 193/253頁(yè)
文件大?。?/td> 1762K
代理商： COLDFIRE2UM
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Test Operation
8-14
ColdFire2/2M User’s Manual
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Clock 5(C5)
TEST_ITAG_WRT must be negated during C5. A1 and D1, associated with C1/C2, are at
the ICACHE tag array during C5; i.e. the actual WRITE to the array occurs in this cycle. The
data value associated with the address asserted in C4, D2, is driven onto MRDATA[31:0]
during this cycle as well. You have the option of driving A2 during this cycle.
Clock 6 (C6)
The TEST_RHIT signal will assert during this cycle if the ICACHE tag array data for A1
matches D1, the access in Cycles C1 and C2; i.e. it is in this cycle that the actual READ
occurs. A2 must be driven onto TEST_ADDR[14:2] during this cycle. TEST_ITAG_WRT
asserts and D2 can optionally be driven during this cycle.
Clock 7 (C7)
On C7, D2, must be driven onto MRDATA[31:0] and the next data RAM address, A3, should
be driven onto TEST_ADDR[14:2]. This is a stall cycle. TEST_ITAG_WRT remains asserted
during this cycle.
Clock 8 (C8)
During C8, TEST_ITAG_WRT must be negated. A3 can optionally be driven during this
cycle; D3 must be driven during this cycle. The actual write of A2/D2 occurs during this
cycle.
This periodic 3-cycle sequence continues; ie. C4-C6 are repeated during C7-C9, C10-C12,
etc. These three cycles are STALL, WRITE, then READ. TEST_ITAG_WRT always negates
during the “C5” cycle or the WRITE cycle and asserts during the “C6-C7” cycles..
TEST_RHIT always asserts if no error during “C6” or the READ cycle. The address is
asserted in the “C4” cycle, optionally asserted in the “C5” cycle and again asserted during
the “C6” cycle. The corresponding data to that address is driven in “C5”, optionally driven in
“C6” and then driven again in “C7”.
8.3.5 Instruction Cache Data RAM Testing
The instruction cache data RAM consists of up to 8K long words that can be accesses
individually through the test bus. Testing the compiled data RAM is accomplished by first
writing test patterns into the data RAM, reading the data RAM, and verifying the results.
8.3.5.1 INSTRUCTION CACHE DATA RAM WRITE FUNCTION.
cache data RAM is performed though the test bus and MRDATA[31:0] after entering test
mode. The address and control signals are input on the test bus and the data to be written
to the data RAM is input on MRDATA[31:0].
Writing to the instruction
Writes to the data RAM are performed in a pipelined fashion as shown in
Figure 8-6
. All input
signals are latched on the positive edge of CLK and all outputs transition on the positive
edge of CLK.
F
Freescale Semiconductor, Inc.
n
.
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