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| 型號(hào)： | COLDFIRE2UM |
| 英文描述： | Version 2/2M ColdFire Core Processor User＇s Manual |
| 中文描述： | 版本2/2M ColdFire內(nèi)核的處理器用戶手冊(cè) |
| 文件頁(yè)數(shù)： | 22/253頁(yè) |
| 文件大小： | 1762K |
| 代理商： | COLDFIRE2UM |
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MOTOROLA
ColdFire2/2M User’s Manual
For More Information On This Product,
Go to: www.freescale.com
1-1
SECTION 1
OVERVIEW
This is a summary of the use and operation of the FlexCore ColdFire microprocessor core
(referred to as the ColdFire2) and FlexCore ColdFire microprocessor core with the Multiply-
Accumulate unit (MAC), referred to as the ColdFire2M. It also contains a detailed set of
timing and electrical specifications. All references to ColdFire2/2M will apply to both the
ColdFire2 and the ColdFire2M devices. Refer to the ColdFire Programmer’s Reference
Manual Rev 1.0(MCF5200PRM/AD) for detailed information on the operation of the
instruction set and addressing modes.
The ColdFire2/2M is part of the FlexCore Program, a semicustom, standard-cell based
design program. Based on the concept of variable-length Reduced Instruction Set Computer
(RISC) technology, ColdFire combines the architectural simplicity of conventional 32-bit
RISC with a memory-saving, variable-length instruction set. In the FlexCore program, high-
volume manufacturers can create their own integrated microprocessor containing a core
processor (such as the ColdFire2/2M) and their own proprietary technology. A FlexCore
integrated processor allows significant reductions in component count, power consumption,
board space, and cost—resulting in higher system reliability and performance.
The main features of the ColdFire2/2M processor include:
32-bit address bus which can directly address up to 4 Gbytes
32-bit data bus
Variable-length RISC
Optimized instruction set for high-level language constructs
Sixteen general-purpose 32-bit data- and address- registers
Multiply Accumulate (MAC) unit for DSP applications (ColdFire2M only)
Supervisor/user modes for system protection
Vector-base register to relocate exception-vector table
Special core interfacing signals for integrated memories
Full debug support
The ColdFire2/2M has 32-bit address and data busses. The 32-bit address bus allows direct
addressing of up to 4 Gbytes. A misalignment unit provides support for misaligned data
accesses, and an optional bus arbitration unit provides support for additional bus masters.
The ColdFire2/2M also supports an integrated instruction cache, SRAM, and ROM
(maximum of 32 Kbyte each.)
F
Freescale Semiconductor, Inc.
n
.
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| COLDFIRE2UMAD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Version 2/2M ColdFire Core Processor User＇s Manual Addendum |
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