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| 型號(hào)： | COLDFIRE2UM |
| 英文描述： | Version 2/2M ColdFire Core Processor User＇s Manual |
| 中文描述： | 版本2/2M ColdFire內(nèi)核的處理器用戶手冊(cè) |
| 文件頁(yè)數(shù)： | 176/253頁(yè) |
| 文件大?。?/td> | 1762K |
| 代理商： | COLDFIRE2UM |
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Debug Support
7-39
ColdFire2/2M User’s Manual
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
BTB[8:9]–Branch Target Bytes
This 2-bit field defines the number of bytes of branch target address to be displayed on the
DDATA
outputs. The encoding is
00 = 0 bytes
01 = lower two bytes of the target address
10 = lower three bytes of the target address
11 = entire four-byte target address
Refer to
Section 7.2.1.5 Begin Execution of Taken Branch (PST = $5)
.
NPL[6]–Non-pipelined Mode
If set, this bit forces the processor core to operate in a nonpipeline mode of operation. In this
mode, the processor effectively executes a single instruction at a time with no overlap.
IPI[5]–Ignore Pending Interrupts
If set, this bit forces the processor core to ignore any pending interrupt requests signalled
while executing in single-instruction-step mode.
SSM[4]–Single-Step Mode
If set, this bit forces the processor core to operate in a single-instruction-step mode. While
in this mode, the processor executes a single instruction and then halts. While halted, any
of the BDM commands may be executed. On receipt of the GO command, the processor
executes the next instruction and then halts again. This process continues until the single-
instruction-step mode is disabled.
Reserved - All bits labelled “Reserved” or “0” are currently unused and are reserved for
future use. These bits should always be written as “0”.
7.4.3 Concurrent BDM and Processor Operation
The debug module supports concurrent operation of both the processor and most BDM
commands. BDM commands may be executed while the processor is running, except for
the operations that access processor/memory registers:
Read/Write Address and Data Registers
Read/Write Control Registers
For BDM commands that access memory, the debug module requests the ColdFire2/2M’s
internal bus. The processor responds by stalling the instruction fetch pipeline and then
waiting until all current bus activity is complete. At that time, the processor relinquishes the
internal bus to allow the debug module to perform the required operation. After the
conclusion of the debug module bus cycle, the processor reclaims ownership of the bus. By
implementing this scheduling mechanism, the processor can minimize the amount of
intrusion caused by debug module requests.
Under certain conditions, the processor may never grant the processor's internal bus to the
debug module causing the BDM command to never be performed. Specifically, the
F
Freescale Semiconductor, Inc.
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| COLDFIRE2UMAD | Version 2/2M ColdFire Core Processor User＇s Manual Addendum |
| COLDFIRE3UM | Version 3 ColdFire Core User＇s Manual |
| COM150A | 100V Single N-Channel Hi-Rel MOSFET in a TO-254AA package |
| COM2017P | UART |
| COM2502P | UART |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| COLDFIRE2UMAD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Version 2/2M ColdFire Core Processor User＇s Manual Addendum |
| COLDFIRE3UM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Version 3 ColdFire Core User＇s Manual |
| COLD-PACK | 制造商:NTE Electronics 功能描述: |
| COLDS/002 | 制造商:Farnell / Duratool 功能描述:JOBBER DRILL SET 1.0-13.0X0.5MM |
| COLINKEX | 制造商:Embest Info&Tech Co Ltd 功能描述:ADAPTER DEBUG SW/JTAG 制造商:EMBEST 功能描述:ADAPTER, DEBUG, SW/JTAG 制造商:EMBEST 功能描述:DEBUGGER, LPC13XX; Silicon Family Name:LPC13xx; Core Architecture:ARM; Core Sub-Architecture:Cortex-M3; IC Product Type:Debugger; Features:Support Cortex M0 and Cortex M3 Devices, Support Software & JTAG Debugging ;RoHS Compliant: Yes |
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