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| 型號(hào)： | COLDFIRE2UM |
| 英文描述： | Version 2/2M ColdFire Core Processor User＇s Manual |
| 中文描述： | 版本2/2M ColdFire內(nèi)核的處理器用戶手冊(cè) |
| 文件頁(yè)數(shù)： | 130/253頁(yè) |
| 文件大?。?/td> | 1762K |
| 代理商： | COLDFIRE2UM |
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Integrated Memories
5-24
ColdFire2/2M User’s Manual
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
If RAM_SZ is set to zero, this bit is set to zero, and the RAM module is disabled. Any attempt
to set the valid bit is disabled when RAM_SZ is set to zero.
5.4.5 RAM Initialization
After a hardware reset, the contents of the RAM module are undefined. The valid bit of the
RAMBAR is cleared, disabling the module. If the RAM needs to be initialized with
instructions or data, the following steps should be performed:
1.
Load the RAMBAR mapping the RAM module to the desired location within the
address space.
2.
Read the source data and write it to the RAM. There are various instructions to
support this function, including memory-to-memory move instructions, or the
MOVEM opcode. The MOVEM instruction is optimized to generate line-sized burst
fetches on 0-modulo-16 addresses, so this opcode generally provides maximum
performance.
3.
After the data has been loaded into the RAM, it may be appropriate to load a revised
value into the RAMBAR with a new set of “attributes”. These attributes consist of the
write-protect and address space mask fields.
These initialization functions can be performed by the ColdFire processor, or from an
external emulator using the debug module.
5.4.6 Power Management
As noted previously, depending upon the configuration defined by the RAMBAR, instruction
fetch accesses may be sent to the RAM module and the I-Cache simultaneously. If the
access is mapped to the RAM module, it sources the read data and the I-Cache access is
discarded. If the RAM is used only for data operands, power dissipation can be lowered by
asserting the ASn bits associated with instruction fetches. Additionally, if the RAM contains
only instructions, power dissipation can be reduced by masking operand accesses.
Consider the following examples of typical RAMBAR settings:
Data contained in RAM
RAMBAR[7:0]
Only code
Only data
Both code and data
$2B
$35
$21
5.5 INTERACTIONS BETWEEN KBUS MEMORIES
Depending on configuration information, instruction fetches and operand accesses may be
sent to all of the K-Bus memories (i.e. RAM, ROM, and ICACHE) simultaneously. There
needs to be consistency between the ACRs and the default modes defined by CACR
(CACR[9], CACR[8], and CACR[5]).
F
Freescale Semiconductor, Inc.
n
.
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| COLDFIRE2UMAD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Version 2/2M ColdFire Core Processor User＇s Manual Addendum |
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