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| 型號(hào)： | COLDFIRE2UM |
| 英文描述： | Version 2/2M ColdFire Core Processor User＇s Manual |
| 中文描述： | 版本2/2M ColdFire內(nèi)核的處理器用戶手冊(cè) |
| 文件頁(yè)數(shù)： | 187/253頁(yè) |
| 文件大?。?/td> | 1762K |
| 代理商： | COLDFIRE2UM |
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Test Operation
8-8
ColdFire2/2M User’s Manual
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
8.3.1.14 TEST WRITE INHIBIT (TEST_WR_INH).
the write strobes to the SRAM and instruction cache compiled RAMS. TEST_WR_INH
should be negated for the duration of memory test.
This active-high input signal disables
8.3.1.15 MIE.
memory arrays. MIE should be asserted for the duration of memory testing.
This active-high input signal enables the capturing of MRDATA into the
8.3.1.16 TR_MODE.
mode. TR_MODE should be negated for the duration of memory testing.
This signal needs to be negated to keep the I/O test ring in functional
8.3.1.17 MWDATA[31:0].
array reads.
The M-Bus write data bus is used to observe array data during
8.3.1.18 MRDATA[31:0].
writes.
The M-Bus read data bus is used to apply write data during array
8.3.1.19 SCAN_MODE.
ColdFire2/2M.
This signal must be negated to allow array output data into the
8.3.1.20 SCAN_SE.
ColdFire2/2M.
This signal must be negated to allow functional operation of the
8.3.1.21 SCAN_XARRAY.
the ColdFire2/2M integrated memories.
This signal should be negated to prevent continuous strobing of
8.3.2 Memory Test Theory of Operation
A write consists of 4 cycles; i.e. it is not until the fourth cycle after applying TEST_ADDR and
MRDATA, with the array’s write control signal active, that data is strobed into the array. Data
and address can be updated continuously every cycle to fill the array via the pipeline.
A read consists of 6 cycles; i.e. it is not until the sixth cycle after applying TEST_ADDR, with
the array’s read control signal active, that data appears on MWDATA. Address can be
updated continuously every cycle to read the array via the pipeline.
Both the SRAM and ICACHE DATA arrays are accessed as noted above. The ROM is read
as noted above. Two test modes exist for the ICACHE TAG array. Essentially the TAG and
DATA array are written. Leaving TEST_MODE asserted, TEST_KTA is then asserted and
address applied. TEST_RHIT will be asserted 4 cycles later, ICACHE DATA array data will
subsequently appear on MWDATA 2 cycles later.
The processor must be placed in reset in accordance with the system reset specification.
The sequence (MRSTB asserted 6 cycles, stall 8cycles) must be executed both upon
entering test mode at power-up, as well as when switching into test mode from any other
mode. It is this sequence that directs the CPU to go into an idle mode to allow integrated
memory testing.
F
Freescale Semiconductor, Inc.
n
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| COLDFIRE2UMAD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Version 2/2M ColdFire Core Processor User＇s Manual Addendum |
| COLDFIRE3UM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Version 3 ColdFire Core User＇s Manual |
| COLD-PACK | 制造商:NTE Electronics 功能描述: |
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| COLINKEX | 制造商:Embest Info&Tech Co Ltd 功能描述:ADAPTER DEBUG SW/JTAG 制造商:EMBEST 功能描述:ADAPTER, DEBUG, SW/JTAG 制造商:EMBEST 功能描述:DEBUGGER, LPC13XX; Silicon Family Name:LPC13xx; Core Architecture:ARM; Core Sub-Architecture:Cortex-M3; IC Product Type:Debugger; Features:Support Cortex M0 and Cortex M3 Devices, Support Software & JTAG Debugging ;RoHS Compliant: Yes |
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