參數(shù)資料
型號(hào)： COLDFIRE2UM
英文描述： Version 2/2M ColdFire Core Processor User＇s Manual
中文描述： 版本2/2M ColdFire內(nèi)核的處理器用戶(hù)手冊(cè)
文件頁(yè)數(shù)： 142/253頁(yè)
文件大?。?/td> 1762K
代理商： COLDFIRE2UM
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Debug Support
MOTOROLA
ColdFire2/2M User’s Manual
For More Information On This Product,
Go to: www.freescale.com
7-5
be dependent on the next instruction in the pipeline. The PST can continue with the next
instruction before the address has completely displayed on the DDATA because of the
DDATA FIFO. If the FIFO is full and the next instruction needs to display something on
DDATA, the pipeline will stall (PST = $0) until space is available in the FIFO.
7.2.1.6 BEGIN EXECUTION OF RTE INSTRUCTION (PST = $7).
generated whenever the return-from-exception instruction is executed.
The unique encoding is
7.2.1.7 BEGIN DATA TRANSFER (PST = $8 - $A).
of bytes to be displayed on the DDATA port on subsequent clock cycles. This encoding is
driven onto the PST port one machine cycle before the actual data is displayed on DDATA.
These encodings indicate the number
7.2.1.8 EXCEPTION PROCESSING (PST = $C).
exception processing. Exceptions which enter emulation mode (debug interrupt, or optional
trace) generate a different encoding. Because this encoding defines a multicycle mode, the
PST outputs are driven with this value until exception processing is completed.
This encoding is displayed during normal
7.2.1.9 EMULATOR-MODE EXCEPTION PROCESSING (PST = $D).
enter emulation mode (debug interrupt, or optional trace) generate a different this encoding.
Because this encoding defines a multicycle mode, the PST outputs are driven with this value
until exception processing is completed.
Exceptions which
7.2.1.10 PROCESSOR STOPPED (PST = $E).
the STOP instruction. The ColdFire2/2M remains in the stopped state until an interrupt
occurs. Because this encoding defines a multicycle mode, the PST outputs are driven with
this value until the stopped mode is exited.
This encoding is generated as a result of
7.2.1.11 PROCESSOR HALTED (PST = $F).
ColdFire2/2M is halted (see
multicycle mode, the PST outputs are driven with this value until the halted mode is exited.
This encoding is generated as when the
Section 7.3.1 CPU Halt
.) Because this encoding defines a
7.3 BACKGROUND DEBUG MODE (BDM)
The ColdFire2/2M supports a modified version of the background debug mode (BDM)
functionality found on Motorola’s CPU32 family of parts. BDM implements a low-level
system debugger in the microprocessor hardware. Communication with the development
system is handled via a dedicated, high-speed serial command interface (BDM port).
Unless noted otherwise, the BDM functionality provided by the ColdFire2/2M is a proper
subset of the CPU32 functionality. The main differences include the following:
ColdFire2/2M implements the BDM controller in a dedicated hardware module.
Although some BDM operations do require the CPU to be halted (e.g. CPU register
accesses), other BDM commands such as memory accesses can be executed while
the processor is running.
DSCLK, DSI, and DSO are treated as synchronous signals, where the inputs, DSCLK
and DSI, must meet the required input setup and hold timings, and the output, DSO, is
specified as a delay relative to the rising edge of the processor clock.
F
Freescale Semiconductor, Inc.
n
.
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