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| 型號(hào)： | XRT94L31IB-L |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 96/133頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MAPPER DS3/E3/STS-1 504TBGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 應(yīng)用： | 網(wǎng)絡(luò)切換 |
| 接口： | 總線 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 封裝/外殼： | 504-LBGA |
| 供應(yīng)商設(shè)備封裝： | 504-TBGA（35x35） |
| 包裝： | 托盤(pán) |
| 安裝類(lèi)型： | 表面貼裝 |
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XRT94L31
65
REV. 1.0.1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
AG18
STS1TXA_2_D6TXH
DLCDAT_2_6TXDS3
DATA_2
I
TTL
Transmit STS-1 Telecom Bus Interface - Channel 2 - Data Input Bus
pin number 6/Transmit High-Speed HDLC Controller Input Interface
block - Channel 2 - Input Data Bus - Pin 6/Transmit DS3/E3 Serial
Data Input - Channel 2:
The function of this pin depends upon whether or not the STS-1 Telecom
Bus Interface, associated with Channel 2 is enabled.
If STS-1 Telecom Bus (Channel 2) has been enabled - Transmit STS-
1 Telecom Bus Interface - Input Data Bus pin number 6 -
STS1TXA_2_D6:
This input pin along with STS1TXA_2_D7 and STS1TXA_2_D[5:0] func-
tion as the Transmit (Add) STS-1 Telecom Bus Interface - Input Data Bus
for Channel 2. The Transmit STS-1 Telecom Bus interface will sample
and latch this pin upon the falling edge of STS1TXA_CLK_2.
If the STS-1 Telecom Bus Interface (associated with Channel 2) has
been disabled:
This input/output pin can function in either of the following roles, depend-
ing upon which mode the XRT94L31 has been configured to operate in,
as described below.
If the XRT94L31 has been configured to operate in the High-Speed
HDLC Controller over DS3/STS-3 Mode - Transmit High-Speed
HDLC Controller Input Interface block - Data Bus Input pin # 6 -
Channel 2 - TXHDLCDAT_2_6:
In this configuration, this input pin will function as Bit 6 within the Trans-
mit High-Speed HDLC Controller Input Interface block - Input Data Bus
(e.g., the TxHDLCDat_2[7:0] input pins).The Transmit High-Speed
HDLC Controller Input Interface block will provide the System-Side Ter-
minal equipment with a byte-wide Transmit High-Speed HDLC Con-
trolller clock output signal (TxHDLCClk_2).
The Transmit High-Speed HDLC Controller Input Interface block will
sample the data residing on this input pin (along with the rest of the
TxHDLCDat_2[7:0] input pins) upon the rising edge of the TxHDLCClk_2
clock output signal.
If the XRT94L31 is configured to operate in the Clear-Channel DS3/
E3 Framer over STS-3/STM-1 Mapper Mode - Transmit Payload Data
Input Interface - Channel 2 - Transmit DS3/E3 Serial Data Input -
TXDS3DATA_2:
In this configuration, this input pin functions as the Transmit Payload
Data Serial Input pin for Channel 2. In this case, the System-Side termi-
nal equipment is expected to apply all outbound data (which is intended
to be carried via the DS3 or E3 payload bits) to this input pin.
The Transmit Payload Data Input Interface will sample the data, residing
at the TxDS3DATA_2 input pin, upon the rising edge of TxInClk.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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