REV. 1.0.1 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC B14 C21 AG15 STS1TXA_DP_n RXDS3POS_n STS1TXA_DP_n RXDS3POS_n STS1TXA_DP_" />
參數(shù)資料
型號(hào): XRT94L31IB-L
廠商: Exar Corporation
文件頁數(shù): 67/133頁
文件大小: 0K
描述: IC MAPPER DS3/E3/STS-1 504TBGA
標(biāo)準(zhǔn)包裝: 24
應(yīng)用: 網(wǎng)絡(luò)切換
接口: 總線
電源電壓: 3.14 V ~ 3.47 V
封裝/外殼: 504-LBGA
供應(yīng)商設(shè)備封裝: 504-TBGA(35x35)
包裝: 托盤
安裝類型: 表面貼裝
XRT94L31
39
REV. 1.0.1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
B14
C21
AG15
STS1TXA_DP_n
RXDS3POS_n
STS1TXA_DP_n
RXDS3POS_n
STS1TXA_DP_n
RXDS3POS_n
I
TTL
STS-1 Transmit Telecom Bus - Parity Input pin/Receive DS3/E3/
STS-1 Positive-Polarity Data Input from LIU - Channel n:
The function of this pin depends upon whether or not the STS-1 Telecom
Bus Interface for Channel n has been enabled.
If STS-1 Telecom Bus (Channel n) has been enabled -
STS1TXA_DP_n - Transmit STS-1 Telecom Bus Interface # n - Parity
Input Pin:
This input pin can be configured to function as one of the following.
To refect either the EVEN or ODD parity value of the bits (within the
incoming STS-1/STS-3/STM-1 data-stream) which are currently being
input via the STS1TXA_D_n[7:0] input pins.
To reflect either the EVEN or ODD parity value of the bits (within the
incoming STS-1/STS-3/STM-1 data-stream) which are being input via
the STS1TXA_D_n[7:0] input, and the states of the STS1TXA_PL_n and
STS1TXA_C1J1_n input pins.
NOTE: The user can make any one of these configuration selections by
writing the appropriate value into the Interface Control Register
- Byte 0 register (Address Location = 0x013B).
If STS-1 Telecom Bus (Channel n) has NOT been enabled -
RXDS3POS_n (Receive DS3/E3/STS-1 Positive-Polarity data input
from LIU)
The DS3/E3 Framer block and the Receive STS-1 TOH Processor block
(associated with Channel n) will sample the data being applied to this
input pin upon the user-selected edge of the RXDS3LINECLK_n input
signal.
If the user has configured Channel n to operate in the STS-1 Mode, or in
the Single-Rail Mode (if also configured to operate in the DS3/E3 Mode),
then all Recovered DS3, E3 or STS-1 data (from the DS3/E3/STS-1 LIU
IC) should be applied to this input pin.
If the user has configured Channel n to operate in both the DS3/E3 and
the Dual-Rail Mode, then only the positive-polarity portion of the Recov-
ered DS3/E3 data output (from the DS3/E3 LIU IC) should be applied to
this input pin.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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