REV. 1.0.1 U2 RXLDAT_R_P I LVPEC L Receive STS-3/STM-1 Data - Positive Polarity PECL" />
參數(shù)資料
型號： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 112/133頁
文件大小： 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
8
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
U2
RXLDAT_R_P
I
LVPEC
L
Receive STS-3/STM-1 Data - Positive Polarity PECL Input - Redun-
dant Port:
This input pin, along with RXLDAT_R_N functions as the Recovered
Data Input, from the Optical Transceiver or as the Receive Data Input
from the system back-plane.
NOTE: For APS (Automatic Protection Switching) purposes, this input
pin, along with RXLDAT_R_N functions as the Redundant
Receive STS-3/STM-1 Data Input Port.
U1
RXLDAT_R_N
I
LVPEC
L
Receive STS-3/STM-1 Data - Negative Polarity PECL Input - Redun-
dant Port:
This input pin, along with RXLDAT_R_P functions as the Recovered
Data Input, from the Optical Transceiver or as the Receive Data Input
from the system back-plane.
NOTE: For APS (Automatic Protection Switching) purposes, this input
pin, along with RXLDAT_R_N functions as the Redundant
Receive STS-3/STM-1 Data Input Port.
AE27
RXCLK_19MHZ
O
CMOS
19.44MHz Recovered Output Clock:
This pin outputs a 19.44MHz clock signal that has been derived from the
incoming STS-3/STM-1 LVPECL line signal (via the Receive STS-3/
STM-1 PECL Interface block) and has been extracted out and derived
by Clock and Data Recovery PLL (within the Receive STS-3/STM-1
PECL Interface block).
To operate the STS-3/STM-1 Interface of the XRT94L31 in the loop-tim-
ing mode, route this particular output signal through a narrow-band PLL
(in order to attenuate any jitter within this signal) prior to routing it to the
REFTTL input pin.
P3
REFCLK_P
I
LVPEC
L
Transmit Reference Clock - Positive Polarity PECL Input:
This input pin, along with REFCLK_N and REFTTL can be configured to
function as the timing source for the STS-3/STM-1 Transmit Interface
Block.
If these two input pins are configured to function as the timing source, a
155.52MHz clock signal must be applied to these input pins in the form
of a PECL signal. Configure these two inputs to function as the timing
source by writing the appropriate data into the Transmit Line Interface
Control Register (Address Location = 0x0383)
NOTE: If REFTTL clock input is used, set this pin to a logic "High"
P2
REFCLK_N
I
LVPEC
L
Transmit Reference Clock - Negative Polarity PECL Input:
This input pin, along with REFCLK_P and REFTTL can be configured to
function as the timing source for the STS-3/STM-1 Transmit Interface
Block.
If these two input pins are configured to function as the timing source,
then the user must apply a 155.52MHz clock signal, in the form of a
PECL signal to these input pins. These two inputscan be configured to
function as the timing source by writing the appropriate data into the
Transmit Line Interface Control Register (Address Location = 0x0383).
NOTE: Set this pin to a logic "Low" if REFTTL clock input is used
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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