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| 型號(hào)： | XRT94L31IB-L |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 50/133頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MAPPER DS3/E3/STS-1 504TBGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 應(yīng)用： | 網(wǎng)絡(luò)切換 |
| 接口： | 總線 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 封裝/外殼： | 504-LBGA |
| 供應(yīng)商設(shè)備封裝： | 504-TBGA（35x35） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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XRT94L31
23
REV. 1.0.1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
D7
TxSDCCEnable
O
CMOS
Transmit - Section DCC Input Port - Enable Output pin:
This output pin, along with the TxTOHClk output pin and the TxSDCC
input pin is used to insert their value for the D1, D2 and D3 bytes, into
the Transmit STS-3 TOH Processor Block. The Transmit STS-3 TOH
Processor block will accept this data and will insert into the D1, D2 and
D3 byte-fields, within the outbound STS-3 data-stream.
The Section DCC HDLC Controller circuitry (which is connected to the
TxTOHClk, the TxSDCC and this output pin, is suppose to do the follow-
ing.
It should continuously monitor the state of this output pin.
Whenever this output pin pulses "High", then the Section DCC HDLC
Controller circuitry should place the next Section DCC bit (to be inserted
into the Transmit STS-3 TOH Processor block) onto the TxSDCC input
pin, upon the rising edge of TxTOHClk.
Any data that is placed on the TxSDCC input pin, will be sampled upon
the falling edge of TxOHClk.
C5
TxSDCC
I
TTL
Transmit - Section DCC Input Port - Input pin:
This input pin, along with the TxSDCCEnable and the TxTOHClk output
pins is used to insert their value for the D1, D2 and D3 bytes, into the
Transmit STS-3 TOH Processor Block. The Transmit STS-3 TOH Pro-
cessor block will accept this data and insert it into the D1, D2 and D3
byte fields, within the outbound STS-3 data-stream.
The Section DCC HDLC Circuitry that is interfaced to this input pin, the
TxSDCCEnable and the TxTOHClk pins is suppose to do the following.
It should continuously monitor the state of the TxSDCCEnable input pin.
Whenever the TxSDCCEnable input pin pulses "High", then the Section
DCC HDLC Controller circuitry should place the next Section DCC bit (to
be inserted into the Transmit STS-3 TOH Processor block) onto this
input pin upon the rising edge of TxTOHClk.
Any data that is placed on the TxSDCC input pin, will be sampled upon
the falling edge of TxTOHClk.Note:
NOTE: This pin should be connected to GND if it is not used.
D8
TxLDCC
I
TTL
Transmit - Line DCC Input Port:
This input pin, along with the TxLDCCEnable and the TxTOHClk pins is
used to insert their value for the D4, D5, D6, D7, D8, D9, D10, D11 and
D12 bytes, into the Transmit STS-3 TOH Processor Block. The Transmit
STS-3 TOH Processor block will accept this data and insert it into the
D4, D5, D6, D7, D8, D9, D10, D11 and D12 byte-fields, within the out-
bound STS-3 data-stream.
Whatever Line DCC HDLC Controller Circuitry is interface to the this
input pin, the TxLDCCEnable and the TxTOHClk is suppose to do the
following.
It should continuously monitor the state of the TxLDCCEnable input pin.
Whenever the TxLDCCEnable input pin pulses "High", then the Section
DCC Interface circuitry should place the next Line DCC bit (to be
inserted into the Transmit STS-3 TOH Processor block) onto the
TxLDCC input pin, upon the rising edge of TxTOHClk.
Any data that is placed on the TxLDCC input pin, will be sampled upon
the falling edge of TxTOHClk.Note:
NOTE: This pin should be connected to GND if it is not used.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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