REV. 1.0.1 AE19 PCS_L I TTL Chip Select Input: This active-low signal must be assert" />
參數(shù)資料
型號： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 90/133頁
文件大?。?/td> 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標準包裝： 24
應用： 網(wǎng)絡切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應商設備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
6
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
AE19
PCS_L
I
TTL
Chip Select Input:
This active-low signal must be asserted in order to select the Micropro-
cessor Interface for READ and WRITE operations between the Micro-
processor and the XRT94L31 on-chip registers, LAPD and Trace Buffer
locations.
AD18
PRDY_L/
DTACK*RDY
O
CMOS
READY or DTACK Output:
The function of this input pin depends upon wich mode the Microproces-
sor Interface has been configured to operate in, as described below.
Intel Asynchronous Mode - RDY* - READY output:
If the Microprocessor Interface has been configured to operate in the
Intel-Asyncrhronous Mode, then this output pin will function as the
active-low READY output.
During a READ or WRITE cycle, the Microprocessor Interface block will
toggle this output pin to the logic "Low" level ONLY when it (the Micro-
processor Interface) is ready to complete or terminate the current READ
or WRITE cycle. Once the Microprocessor has determined that this
input pin has toggled to the logic "Low" level, then it is now safe for it to
move on and execute the next READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor Interface block is
holding this output pin at a logic "High" level, then the MIcroprocessor is
expected to extend this READ or WRITE cycle, until it detect this output
pin being toggled to the logic "Low" level.
Motorola Mode - DTACK* - Data Transfer Acknowledge Output:
If the Microprocessor Interface has been configured to operate in the
Motorola-Asynchronous Mode, then this output pin will function as the
active-low DTACK* ouytput.
During a READ or WRITE cycle, the Microprocessor Interface block will
toggle this output pin to the logic "Low" level, ONLY when it (the Micro-
processor Interface) is ready to complete or terminate the current READ
or WRITE cycle. Once the Microprocessor has determined that this
input pin has toggled to the logic "Low" leve, then it is now safe for it to
move on and execute the next READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor Interface block is
holding this output pin at a logic "High" level, then the MIcroprocessor is
expected to extend this READ or WRITE cycle, until it detects this output
pin being toggled to the logic "Low" level.
PowerPC 403 Mode - RDY - Ready Output:
If the Microprocessor Interface has been configured to operate in the
PowerPC 403 Mode, then this output pin will function as the active-high
READY output.
During a READ or WRITE cycle, the Microprocessor Interface block will
toggle this output pin to the logic "High" level, ONLY when the Micropro-
cessor Interface is ready to complete or terminate the current READ or
WRITE cycle. Once the Microprocessor has sampled this signal being
at a logic "High" level (upon the rising edge of PCLK) then it is now safe
for it to move on and execute the next READ or WRITE cycle.
The Microprocessor Interface will update the state of this output pin upon
the rising edge of PCLK.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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