REV. 1.0.1 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC E14 c22 AD14 STS1TXA_PL_0 TXSENDMSG_0 STS1TXA_PL_n TXSENDMSG_n STS1TXA_P" />
參數(shù)資料
型號： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 65/133頁
文件大?。?/td> 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
37
REV. 1.0.1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
E14
c22
AD14
STS1TXA_PL_0
TXSENDMSG_0
STS1TXA_PL_n
TXSENDMSG_n
STS1TXA_PL_n
TXSENDMSG_n
I
TTL
STS-1 Transmit Telecom Bus - Payload Indicator Signal input/
Transmit High-Speed HDLC Controller Input Interface block - Send
Message Command Input pin - Channel n (n=0, 1, 2):
The function of this input depends upon whether or not the STS-1 Tele-
com Bus Interface for Channel n has been enabled.
If STS-1 Telecom Bus (Channel n) has been enabled -
STS1TXA_PL_n - Transmit STS-1 Telecom Bus Interface - Payload
Indicator Input Signal - Channel n:
This input pin indicates whether or not Transport Overhead (TOH) bytes
are being input via the TXA_D_n[7:0] input pins.
This input pin should be pulled "Low" for the duration that the Transmit
STS-1 Telecom Bus Interface is accepting a TOH byte, via the
TXA_D_n[7:0] input pins. Conversely, this input pin should be pulled
"High" at all other times.
NOTE:
This input signal is sampled upon the falling edge of
STS1TXA_CK_n.
If STS-1 Telecom Bus (Channel n) has NOT been enabled:
If STS-1 Telecom Bus (Channel n) has not been enabled, then this par-
ticular pin can either be configured to function as the TxSENDMSG_n
input pin (if the DS3/E3 Framer block within Channel n has been config-
ured to operate in the High-Speed HDLC Controller Mode), or the user
should simply tie this input pin to GND. The details of this pin's role as
the TxSENDMSG_n input pin is described below.
If STS-1 Telecom Bus (Channel n) is disabled: TXSENDMSG_n
(:Transmit High-Speed HDLC Controller Input Interface block -
Send Message Command Input - Channel n - High-Speed HDLC
Controller Mode Only)
This input pin is used to command the Transmit High-Speed HDLC Con-
troller Input Interface block (associated with Channel n) to begin sam-
pling and latching the data which is being applied to the
TxHDLCDat_n[7:0] input pins.
If the user pulls this input pin "High", then the Transmit High-Speed
HDLC Controller block samples and latches the data which is applied to
the TxHDLCDat_n[7:0] input pins upon the rising edge of TxHDLCClk_n.
Each byte of this sampled data will ultimately be encapsulated into an
outbound HDLC frame and will be mapped into the payload bits within
the outbound DS3/E3 frames via the DS3/E3 Framer block.
If the user pulls this input pin "Low" then the Transmit High-Speed HDLC
Controller block will NOT sample and latch the contents on the
TxHDLCDat_n[7:0] input pins, and the Transmit High-Speed HDLC Con-
troller block will simply generate a continuous stream of flag sequence
octets (0x7E).
NOTE: If the DS3/E3 Framer block has NOT been configured to operate
in the High-Speed HDLC Controller Mode, tie this pin to GND.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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