REV. 1.0.1 E18 STS1TXA_1_D3 TXHDLCDAT_1_3 SSI_POS I/O TTL/ CMOS Transmit STS-1 Tele" />
參數(shù)資料
型號： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 84/133頁
文件大小： 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
54
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
E18
STS1TXA_1_D3
TXHDLCDAT_1_3
SSI_POS
I/O
TTL/
CMOS
Transmit STS-1 Telecom Bus Interface - Channel 1 - Data Bus Input
pin number 3/Transmit High-Speed HDLC Controller Input Interface
block - Channel 1 - Input Data Bus - Pin 3/Slow-Speed Interface -
Positive Polarity Data Input/Output signal:
The function of this pin depends upon whether or not the STS-1 Telecom
Bus Interface, associated with Channel 1 is enabled.
If STS-1 Telecom Bus (Channel 1) has been enabled -Transmit STS-
1 Telecom Bus Interface - Input Data Bus pin number 3:
STS1TXA_1_D3:
This input pin along with STS1TXA_1_D[7:4] and STS1TXA_1_D[2:0]
function as the Transmit (Add) STS-1 Telecom Bus Interface - Input Data
Bus for Channel 1. The Transmit STS-1 Telecom Bus interface will sam-
ple and latch this pin upon the falling edge of STS1TXA_CLK_1.
If the STS-1 Telecom Bus Interface (associated with Channel 1) has
been disabled:
This input/output pin can function in either of the following roles, depend-
ing upon which mode the XRT94L31 has been configured to operate in.
If the XRT94L31 has been configured to operate in the High-Speed
HDLC Controller over DS3/STS-3 Mode - Transmit High-Speed
HDLC Controller Input Interface block - Channel 1 - Data Bus Input
pin # 3 - TXHDLCDAT_1_3:
In this mode this input pin will function as Bit 3 within the Transmit High-
Speed HDLC Controller Input Interface block - Input Data Bus (e.g., the
TxHDLCDat_1[7:0] input pins).
The Transmit High-Speed HDLC Controller Input Interface block will pro-
vide the System-Side Terminal equipment with a byte-wide Transmit
High-Speed HDLC Controlller clock output signal (TxHDLCClk_1). The
Transmit High-Speed HDLC Controller Input Interface block will sample
the data residing on this input pin (along with the rest of the
TxHDLCDat_1[7:0] input pins) upon the rising edge of the TxHDLCClk_1
clock output signal.
If the XRT94L31 is configured to operate in the DS3/E3/STS-1 to
STS-3/STM-1 Mapper Mode - Slow Speed Interface for Ingress Path
- Positive-Polarity Data Input/Output - SSI_POS:
This pin along with the SSI_NEG and SSI_CLK pins function as the
Slow-Speed Interface for the Ingress Direction Signal Path Input/Output
Port and can be configured to function as either an Input (ADD) or Out-
put (DROP) port.
If the SSI Port is configured to operate as an Input (ADD) Port:
Then this port can be configured to accept a DS3, E3 or STS-1 signal
(from external circuitry) and it will ADD this DS3/E3/STS-1 signal into the
Selected Ingress Direction Channel within the XRT94L31. In this mode,
the SSI_POS will function as the Positive-Polarity Portion of the DS3/E3/
STS-1 signal that is being ADDed. In this mode, the SSI Port will sample
the data (being applied to this pin) upon the rising edge of SSI_CLK.
If the SSI Interface is configured to operate as an Output (DROP)
Port:
Then this port can be configured to output (or DROP out) the Selected
Ingress Direction Channel within the XRT94L31.In this mode the
SSI_POS will output the Positive Polarity portion of this selected Ingress
Direction signal. This output pin will be updated upon the falling edge of
the SSI_CLK output pin.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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