REV. 1.0.1 1.3.5 Ingress Timing for STS-1/STM-0 Applications Table 13 presents inf" />
參數(shù)資料
型號： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 16/133頁
文件大?。?/td> 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
112
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
1.3.5
Ingress Timing for STS-1/STM-0 Applications
Table 13 presents information on the Timing parameters for the DS3/E3/STS-1 LIU Interface Signals (in the
Ingress Direction) for STS-1/STM-0 Applications and when the Receive STS-1 TOH Processor block has been
configured to sample the DS3/E3/STS_1_DATA_IN signal upon the rising edge of DS3/E3/
STS_1_CLOCK_IN.
Table 14 presents information on the Timing parameters for the DS3/E3/STS-1 LIU Interface Signals (in the
Ingress Direction) for STS-1/STM-0 Applications and when the Receive STS-1 TOH Processor block has been
configured to sample the DS3/E3/STS_1_DATA_IN signal upon the falling edge of DS3/E3/
STS_1_CLOCK_IN.
1.3.6
The Egress DS3/E3/STS-1 Interface Timing
The user should be aware of the followings things about the Egress DS3/E3/STS-1 Interface timing.
a. If a given channel is configured to operate in the DS3/E3 Mode, then the DS3/E3 Framer block can be
configured to output the outbound DS3/E3 data (via the DS3/E3/STS_1_DATA_OUT and DS3/E3/
STS_1_NEG_OUT output pins) upon either the rising or falling edge of DS3/E3/STS_1_CLOCK_OUT.
b. If a given channel is configured to operate in the STS-1/STM-0 Mode, then the Transmit STS-1 TOH
Processor block will be operating in the Single-Rail Mode (e.g., the Transmit STS-1 TOH Processor block
will output all outbound STS-1/STM-0 data via the DS3/E3/STS_1_DATA_OUT output pin. No data will be
output via the DS3/E3/STS_1_NEG_OUT output pin).
c. Further, if a given channel is configured to operate in the STS-1/STM-0 Mode, then the Transmit STS-1
TOH Processor block can be configured to output the outbound STS-1/STM-0 data (via the DS3/E3/
STS_1_DATA_OUT pin) either upon the rising or falling edge of DS3/E3/STS_1_CLOCK_OUT.
The Timing Diagram for the Egress DS3/E3/STS-1 Interface is presented below in Figure 17.
TABLE 13: TIMING INFORMATION FOR THE INGRESS DS3/E3/STS-1 LIU INTERFACE FOR STS-1/STM-0
APPLICATIONS(RISING EDGE OF DS3/E3/STS_1_CLOCK_IN)
SYMBOL
DESCRIPTION
MIN.
TYP.
MAX.
t9
DS3/E3/STS_1_DATA_IN to rising edge of DS3/E3/STS_1_CLOCK_IN
set-up time requirements
4ns
t10
Rising edge of DS3/E3/STS_1_CLK_IN to DS3/E3/STS_1_DATA_IN and
DS3/E3/STS_1_CLOCK_IN Hold time requirements
0ns
TABLE 14: TIMING INFORMATION FOR THE INGRESS DS3/E3/STS-1 LIU INTERFACE FOR STS-1/STM-0
APPLICATIONS(FALLING EDGE OF DS3/E3/STS_1_CLOCK_IN)
SYMBOL
DESCRIPTION
MIN.
TYP.
MAX.
t9
DS3/E3/STS_1_DATA_IN to falling edge of DS3/E3/STS_1_CLOCK_IN
set-up time requirements
4ns
t10
Falling edge of DS3/E3/STS_1_CLK_IN to DS3/E3/STS_1_DATA_IN and
DS3/E3/STS_1_CLOCK_IN Hold time requirements
0ns
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