REV. 1.0.1 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC A5 A6 A7 TxPOHClk_0 TxPOHClk_1 TxPOHClk_2 O CMOS Transmit Path Overhead " />
參數(shù)資料
型號(hào)： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 54/133頁
文件大小： 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
27
REV. 1.0.1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
A5
A6
A7
TxPOHClk_0
TxPOHClk_1
TxPOHClk_2
O
CMOS
Transmit Path Overhead Input Port - Clock Output pin:
These output pins, along with TxPOH_n, TxPOHEnable_n, TxPOHIns_n
and TxPOHFrame function as the Transmit Path Overhead (TxPOH)
Input Port.
The TxPOHFrame and TxPOHEnable output pins are updated upon the
falling edge this clock output signal. The TxPOHIns_n input pins and the
data residing on the TxPOH_n input pins are sampled upon the next fall-
ing edge of this clock signal.
C9
C10
A8
TxPOHFrame_0
TxPOHFrame_1
TxPOHFrame_2
O
CMOS
Transmit Path Overhead Input Port - Frame Output pin:
These output pins, along with the TxPOH_n, TxPOHEnable_n,
TxPOHIns_n and TxPOHClk_n function as the Transmit Path Overhead
Input Port.The function of these output pins depends upon whether or
not the user inserting POH or TOH data via the TxPOH_n input pins.If
the user is only inserting POH data via these input pins:The TxPOH port
will pulse these output pins "High" whenever it is ready to accept and
process the J1 byte (e.g., the very first POH byte) via this port.
NOTES:
1. The externally circuitry can determine whether or not the
TxPOH port is expecting the A1 byte or the J1 byte, by
checking the state of the corresponding TxPOHEnable output
pin.
If the TxPOHEnable_n output pin is "Low" while the
TxPOHFrame_n output pin is "High", then the TxPOH port is
ready to process the A1 (TOH) bytes.
2. If the TxPOHEnable_n output pin is "High" while the
TxPOHFrame_n output pin is "High", then the TxPOH port is
ready to process the J1 (POH) bytes.
D10
E11
C11
TxPOHIns_0
TxPOHIns_1
TxPOHIns_2
I
TTL
Transmit Path Overhead Input Port - Insert Enable Input pin:
These input pins, along with TxPOH_n, TxPOHEnable_n,
TxPOHFrame_n and TxPOHClk_n function as the Transmit Path Over-
head (TxPOH) Input Port.
These input pins are used to enable or disable the TxPOH input port. If
these input pins are pulled "High", then the TxPOH port will sample and
latch data via the corresponding TxPOH input pins, upon the falling edge
of TxPOHClk_n.
Conversely, if these input pins are pulled "Low", then the TxPOH port will
NOT sample and latch data via the corresponding TxPOH input
pins.Note:
NOTE: If the TxPOHIns_n input pin is pulled "Low", this setting will be
overridden if the user has configured the Transmit SONET/STS-
1 POH Processor or Transmit STS-1 TOH Processor blocks to
accept certain POH or TOH overhead bytes via the external
port.
B7
B9
B10
TxPOHEnable_0
TxPOHEnable_1
TxPOHEnable_2
O
CMOS
Transmit Path Overhead Input Port - POH Indicator Output pin:
These output pins, along with TxPOH_n, TxPOHIns_n, TxPOHFrame_n
and TxPOHClk_n function as the Transmit Path Overhead (TxPOH)
Input Port.
These output pins will pulse "High" anytime the TxPOH port is ready to
accept and process POH bytes. These output pins will be "Low" at all
other times.
TRANSMIT LINE/ SYSTEM SIDE INTERFACE PINS
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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