REV. 1.0.1 AG4 RXPOHCLK O CMOS Receive AU-4/VC-4/STS-3c Mapper POH Processor Block " />
參數(shù)資料
型號： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 119/133頁
文件大?。?/td> 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
86
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
AG4
RXPOHCLK
O
CMOS
Receive AU-4/VC-4/STS-3c Mapper POH Processor Block - Path
Overhead Output Port - Clock Output Signal:
This output pin, along with RxPOH, RxPOHFrame and RxPOHValid
function as the AU-4/VC-4 Mapper POH Processor block - POH Output
Port.
These output pins function as the Clock Output signals for the AU-4/VC-
4 Mapper POH Processor Block- POH Output Port. The RxPOH, RxPO-
HFrame and RxPOHValid output pins are updated upon the falling edge
of this clock signal. As a consequence, the external circuitry should
sample these signals upon the rising edge of this clock signal.
AE7
RXPOHFRAME
O
CMOS
Receive AU-4/VC-4/STS-3c Mapper POH Processor Block - Path
Overhead Output Port - Frame Boundary Indicator:
This output pin, along with the RxPOH, RxPOHClk and RxPOHValid out-
put pins function as the AU-4/VC-4 Mapper POH Processor Block - Path
Overhead Output Port.
These output pins will pulse "High" coincident with the very first POH
byte (J1), of a given STS-1 frame, is being output via the corresponding
RxPOH output pin.
AD9
RXPOHVALID
O
CMOS
Receive AU-4/VC-4/STS-3c Mapper POH Processor Block - Path
Overhead Output Port - Valid POH Data Indicator:
This output pin, along with RxPOH, RxPOHClk and RxPOHFrame func-
tion as the AU-4/VC-4 Mapper POH Processor block - Path Overhead
Output port.
These output pins will toggle "High" coincident with when valid POH data
is being output via the RxPOH output pins. This output is updated upon
the falling edge of RxPOHClk. Hence, external circuitry should sample
these signals upon rising edge of RxPOHClk.
AF5
AG5
AF8
RxPOH_0
RxPOH_1
RxPOH_2
O
CMOS
Receive SONET POH Processor Block - Path Overhead Output Port
- Output Pin:
These output pins, along with the RxPOHClk_n, RxPOHFrame_n and
RxPOHValid_n function as the Receive SONET POH Processor block -
POH Output port.
These pins serially output the POH data that have been received by
each of the Receive SONET POH Processor blocks (via the incoming
STS-3 data-stream). Each bit, within the POH bytes is updated (via
these output pins) upon the falling edge of RxPOHClk_n. As a conse-
quence, external circuitry receiving this data, should sample this data
upon the rising edge of RxPOHClk_n.
AE8
AE9
AG6
RxPOHClk_0
RxPOHClk_1
RxPOHClk_2
O
CMOS
Receive SONET POH Processor Block - Path Overhead Output Port
- Clock Output Signal:
These output pins, along with RxPOH_n, RxPOHFrame_n and
RxPOHValid_n function as the Receive SONET POH Processor block -
POH Output Port.
These output pins function as the Clock Output signals for the Receive
SONET POH Processor block - POH Output Port. The RxPOH_n,
RxPOHFrame_n and RxPOHValid_n output pins are updated upon the
falling edge of this clock signal. As a consequence, the external circuitry
should sample these signals upon the rising edge of this clock signal.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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