REV. 1.0.1 B21 STS1TXA_1_D7TXH DLCDAT_1_7TXAISE N_1 I TTL Transmit STS-1 Telecom Bu" />
參數(shù)資料
型號： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 88/133頁
文件大?。?/td> 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
58
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
B21
STS1TXA_1_D7TXH
DLCDAT_1_7TXAISE
N_1
I
TTL
Transmit STS-1 Telecom Bus Interface - Channel 1 - Input Data Bus
pin number 7/Transmit High-Speed HDLC Controller Input Interface
block - Channel 2 - Input Data Bus - Pin 7/Transmit DS3/E3 AIS
Input Pin - Channel 1:
The function of this pin depends upon whether or not the STS-1 Telecom
Bus Interface, associated with Channel 1 is enabled.
If STS-1 Telecom Bus (Channel 1) has been enabled -Transmit STS-
1 Telecom Bus Interface - Input Data Bus pin number 7:
STS1TXA_1_D7:
This input pin along with STS1TXA_1_D[6:0] function as the Transmit
(Add) STS-1 Telecom Bus Interface - Input Data Bus for Channel 1. The
Transmit STS-1 Telecom Bus interface will sample and latch this pin
upon the falling edge of STS1TXA_CLK_1.
NOTE: This input pin functions as the MSB (Most Significant Bit) of the
Transmit (Add) Telecom Bus, for Channel 1.
If the STS-1 Telecom Bus (associated with Channel 1) has been dis-
abled:
This input/output pin can function in either of the following roles, depend-
ing upon which mode the XRT94L31 has been configured to operate in,
as described below.
If the XRT94L31 has been configured to operate in the High-Speed
HDLC Controller over DS3/STS-3 Mode - Transmit High-Speed
HDLC Controller Input Interface block - Data Bus Input Pin # 7 -
Channel 1 -TXHDLCDAT_1_7:
This input pin will function as Bit 5 within the Transmit High-Speed HDLC
Controller Input Interface block - Input Data Bus (e.g., the
TxHDLCDat_1[7:0] input pins).
The Transmit High-Speed HDLC Controller Input Interface block will pro-
vide the System-Side Terminal equipment with a byte-wide Transmit
High-Speed HDLC Controlller clock output signal (TxHDLCClk_1).
The Transmit High-Speed HDLC Controller Input Interface block will
sample the data residing on this input pin (along with the rest of the
TxHDLCDat_1[7:0] input pins) upon the rising edge of the TxHDLCClk_1
clock output signal.
If the XRT94L31 is configured to operate in any other mode that
involves the DS3/E3 Framer block - Transmit DS3/E3 AIS Enable
Input - Channel 1 - TXAISEN_1:T
his input pin is used to command the Frame Generator block (within
Channel 1) to generate and transmit the DS3/E3 AIS pattern, as
described below.
"Low" - Configures the Frame Generator block to NOT generate and
transmit the DS3/E3 AIS Pattern
"High" - Configures the Frame Generator block to generate and
transmit the DS3/E3 AIS Pattern
NOTE: If the transmission of DS3/E3 AIS is controlled via Software, then
this input pin MUST be tied to GND
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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