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| 型號： | XRT94L31IB-L |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 49/133頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MAPPER DS3/E3/STS-1 504TBGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 應(yīng)用： | 網(wǎng)絡(luò)切換 |
| 接口： | 總線 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 封裝/外殼： | 504-LBGA |
| 供應(yīng)商設(shè)備封裝： | 504-TBGA（35x35） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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XRT94L31
22
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
D6
TxTOHIns
I
TTL
Transmit TOH Input Port - Insert Enable Input pin:
This input pin, along with the TxTOH input pin, and the TxTOHEnable,
TxTOHFrame and TxTOHClk output pins function as the Transmit TOH
Input Port.
This input pin is used to either enable or disable the Transmit TOH Input
Port.
If this input pin is "Low", then the Transmit TOH Input Port will be dis-
abled and will not sample and insert (into the outbound STS-3 data
stream) any data residing on the TxTOH input, upon the rising edge of
TxTOHClk.
If this input pin is "High", then the Transmit TOH Input Port will be
enabled. In this mode, whenever the TxTOHEnable output pin is also
"High", the Transmit TOH Input Port will sample and latch any data that
is presented on the TxTOH input pin, upon the rising edge of TxTOHClk.
To externally insert user values of TOH into the outbound STS-3 data
stream via the Transmit TOH Input Port, do the following.
Continuously sample the state of TxTOHFrame and TxTOHEnable
upon the rising edge of TxTOHClk.
Whenever the TxTOHEnable output pin is sampled "High" then the
user's external circuitry should drive this input pin "High".
Next, output the next TOH bit, onto the TxTOH input pin, upon the
falling edge of TxTOHClk. The Transmit TOH Input Port will sample
the data (on this input pin) upon the falling edge of TxTOHClk.]
NOTES:
1. Data applied to the TxTOH input pin will be sampled according
to the following insertion priority scheme:
2. For DCC, E1, F1, E2 bytes, TxTOH input pin will be sampled if
both TxTOHEnable and TxTOHIns are "High".
3. For other TOH bytes, TxTOH input pin will be sampled if both
TxTOHEnable and TxTOHIns are "High" or if both TxTOHIns
and Software Insertion Enabled are "Low".
B4
TxLDCCEnable
O
CMOS
Transmit - Line DCC Input Port - Enable Output pin:
This output pin, along with the TxTOHClk output pin and the TxLDCC
input pin are used to insert their value for the D4, D5, D6, D7, D8, D9,
D10, D11 and D12 bytes into the Transmit STS-3 TOH Processor Block.
The Transmit STS-3 TOH Processor block will accept this data and will
insert into the D4, D5, D6, D7, D8, D9, D10, D11 and D12 byte-fields,
within the outbound STS-3 data-stream.
The Line DCC HDLC Controller circuitry (which is connected to the
TxTOHClk, the TxSDCC and this output pin, is suppose to do the follow-
ing.
It should continuously monitor the state of this output pin.
Whenever this output pin pulses "High", then the Line DCC HDLC Con-
troller circuitry should place the next Line DCC bit (to be inserted into the
Transmit STS-3 TOH Processor block) onto the TxLDCC input pin, upon
the rising edge of TxTOHClk.
Any data that is placed on the TxLDCC input pin, will be sampled upon
the falling edge of TxOHClk.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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