REV. 1.0.1 C12 B20 AF17 TXDS3CLK_0 TXE3CLK_0 TXDS3CLK_1 TXE3CLK_1 TXDS3CLK_2 TXE3CL" />
參數(shù)資料
型號： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 55/133頁
文件大小： 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
28
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
C12
B20
AF17
TXDS3CLK_0
TXE3CLK_0
TXDS3CLK_1
TXE3CLK_1
TXDS3CLK_2
TXE3CLK_2
I
TTL
Transmit DS3/E3 Reference Clock Input - Channel_n (Not used for
Mapper Applications):n=[0:2]
The manner in which the user should handle this input pin depends upon
whether Channe_n has been configured to operate in the Mapper Mode
or in the ATM UNI/PPP Mode.
If Channel_n is configured to operate in the Mapper Mode:
If Channel_n has been configured to operate in the Mapper Mode, then
this input pin supports no function, and should, therefore, be connected
to GND.
If Channel_n is configured to operate in the ATM UNI/PPP/Clear
Channel Mode:
If Channel_n (within the XRT94L31) has been configured to operate in
the ATM UNI/PPP Mode, then this input pin will function as the timing
reference clock signal for the Transmit STS-1/DS3/E3 Framer block cir-
cuitry, provided that Channel_n has been configured to operate in the
Local Timing Mode.
If Channel_h has been configured to operate in the DS3 Mode, then the
user is expected to apply a 44.736MHz clock signal to this input pin.
Likewise, if Channel_n has been configured to operate in the E3 Mode,
then the user is expected to apply a 34.368MHz clock signal to this input
pin.
NOTE: For more information on using the XRT94L31 for ATM UNI/PPP
applications, the user should consult the XRT94L31 1-Channel
STS-3c/3-Channel DS3/E3/STS-1 ATM UNI/PPP Data Sheet.
B11
A22
AD16
TxOHClk_0
TxOHClk_1
TxOHClk_2
O
CMOS
Transmit Overhead Clock Output:
This output pin functions as the Transmit Overhead Clock output for the
transmit system side interface when the XRT94L31 is configured to
operate in STS-1/DS3/E3 mode, however, it functions as the Transmit
STS-1 Overhead clock output when the device is configured to operate
in the STS-1 mode.
When configured to operate in DS3/E3 mode:
This output pin functions as the Transmit Overhead Data Input Interface
clock signal. If the user enables the Transmit Overhead Data Input Inter-
face block by asserting the TxOHIns input pin, then the Transmit Over-
head Data Input Interface block will sample and latch the data (residing
on the TxOH_n input pin) upon the falling edge of this signal.
When configured to operate in STS-1 mode:
These output pins, along with TxOH_n, TxOHEnable_n, TxOHIns_n and
TxOHFrame function as the Transmit Path Overhead (TxOH) Input Port.
The TxOHFrame and TxOHEnable output pins are updated upon the
falling edge this clock output signal. The TxOHIns_n input pins and the
data residing on the TxOH_n input pins are sampled upon the falling
edge of this clock signal.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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