REV. 1.0.1 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC A23 STS1TXA_1_D4 TXHDLCDAT_1_4 TXDS3OHIND_1 I/O TTL/ CMOS Transmit STS-1" />
參數(shù)資料
型號： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 85/133頁
文件大?。?/td> 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標準包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
55
REV. 1.0.1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
A23
STS1TXA_1_D4
TXHDLCDAT_1_4
TXDS3OHIND_1
I/O
TTL/
CMOS
Transmit STS-1 Telecom Bus Interface - Channel 1 - Input Data Bus
Input pin number 4/Transmit High-Speed HDLC Controller Input
Interface block -Channel 1 - Input Data Bus - Pin 4/Transmit DS3/E3
Overhead Indicator Output - Channel 1:
The function of this pin depends upon whether or not the STS-1 Telecom
Bus Interface, associated with Channel 1 is enabled.
If STS-1 Telecom Bus (Channel 1) has been enabled - Transmit STS-
1 Telecom Bus Interface - Input Data Bus pin number 4:
STS1TXA_1_D4:
This input pin along with STS1TXA_1_D[7:5] and STS1TXA_1_D[3:0]
function as the Transmit (Add) STS-1 Telecom Bus Interface - Input Data
Bus for Channel 1. The Transmit STS-1 Telecom Bus interface will sam-
ple and latch this pin upon the falling edge of STS1TXA_CLK_1.
If the STS-1 Telecom Bus Interface (associated with Channel 1) has
been disabled:
This input/output pin can function in either of the following roles, depend-
ing upon which mode the XRT94L31 has been configured to operate in.
If the XRT94L31 has been configured to operate in the High-Speed
HDLC Controller over DS3/STS-3 Mode - Transmit High-Speed
HDLC Controller Input Interface block - Channel 1 - Data Bus Input
pin # 4 - TxHDLCDAT_1_4:
Then this input pin will function as Bit 4 within the Transmit High-Speed
HDLC Controller Input Interface block - Input Data Bus (e.g., the
TxHDLCDat_1[7:0] input pins).
The Transmit High-Speed HDLC Controller Input Interface block will pro-
vide the System-Side Terminal equipment with a byte-wide Transmit
High-Speed HDLC Controlller clock output signal (TxHDLCClk_1).
The Transmit High-Speed HDLC Controller Input Interface block will
sample the data residing on this input pin (along with the rest of the
TxHDLCDat_1[7:0] input pins) upon the rising edge of the TxHDLCClk_1
clock output signal.
If the XRT94L31 is configured to operate in the Clear-Channel DS3/
E3 Framer over STS-3/STM-1 Mapper Mode - Transmit DS3/E3 Over-
head Indicator Output - Channel 1 - TXDS3OHIND_1:
This output pin will pulse "High" one bit-period prior to the time that the
DS3/E3 Frame Generator block (within Channel 1) will be processing an
Overhead bit. The purpose of this outpout pin is to warn the Terminal
Equipment that, during the very next bit-period, the DS3/E3 Frame Gen-
erator block is going to be processing an Overhead Bit and will be ignor-
ing any data that is applied to to the TxDS3DATA_1 input pin.
NOTE: This output pin can be ignored providing that either the Primary
or Secondary Frame Synchronizer block is always up-stream
from the DS3/E3 Frame Generator block.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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