REV. 1.0.1 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC AB8 RxTOHFrame O CMOS Receive TOH Output Port - STS-3/STM-1 Frame Indica" />
參數(shù)資料
型號： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 116/133頁
文件大?。?/td> 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
83
REV. 1.0.1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
AB8
RxTOHFrame
O
CMOS
Receive TOH Output Port - STS-3/STM-1 Frame Indicator:
This output pin, along with the RxTOHClk, RxTOHValid and RxTOH out-
put pins function as the Receive TOH Output port.
This output pin will pulse "High", for one period of RxTOHClk, one RxTO-
HClk period prior to the very first TOH bit (of a given STS-3 frame) being
output via the RxTOH output pin.
AD7
RxLDCCVAL
O
CMOS
Receive - Line DCC Output Port - DCC Value Indicator Output pin:
This output pin, along with the RxTOHClk and the RxLDCC output pins
function as the Receive Line DCC output port of the XRT94L31.
This output pin pulses "High" coincident to when the Receive Line DCC
output port outputs a DCC bit via the RxLDCC output pin.
This output pin is updated upon the falling edge of RxTOHClk.
The Line DCC HDLC Controller circuitry that is interfaced to this output
pin, the RxLDCC and the RxTOHClk pins is suppose to do the following.
It should continuously sample and monitor the state of this output pin
upon the rising edge of RxTOHClk.
Anytime the Line DCC HDLC circuitry samples this output pin being
"High", it should sample and latch the data on the RxLDCC output pin
(as a valid Line DCC bit) into the Line DCC HDLC circuitry.
AE5
RxLDCC
O
CMOS
Receive - Line DCC Output Port - Output Pin:
This output pin, along with RxLDCCVAL and the RxTOHClk output pins
function as the Receive Line DCC output port of the XRT94L31.
This pin outputs the contents of the Line DCC (e.g., the D4, D5, D6, D7,
D8, D9, D10, D11 and D12 bytes), within the incoming STS-3 data-
stream.
The Receive Line DCC Output port will assert the RxLDCCVAL output
pin, in order to indicate that the data, residing on the RxLDCC output pin
is a valid Line DCC byte. The Receive Line DCC output port will update
the RxLDCCVAL and the RxLDCC output pins upon the falling edge of
the RxTOHClk output pin.
The Line DCC HDLC circuitry that is interfaced to this output pin, the
RxLDCCVAL and the RxTOHClk pins is suppose to do the following.
It should continuously sample and monitor the state of the RxLDCCVAL
output pin upon the rising edge of RxTOHClk.
Anytime the Line DCC HDLC circuitry samples the RxLDCCVAL output
pin "High", it should sample and latch the contents of this output pin (as
a valid Line DCC bit) into the Line DCC HDLC circuitry.
AD8
RxE1F1E2FP
O
CMOS
Receive - Order-Wire Output Port - Frame Boundary Indicator:
This output pin, along with RxE1F1E2, RxE1F1E2Val and the RxTOHClk
output pins function as the Receive Order-Wire Output port of the
XRT94L31.
This output pin pulses "High" (for one period of RxTOHClk) coincident to
when the very first bit (of the E1 byte) is being output vi the RxE1F1E2
output pin.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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