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| 型號(hào)： | XRT94L31IB-L |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 43/133頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MAPPER DS3/E3/STS-1 504TBGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 應(yīng)用： | 網(wǎng)絡(luò)切換 |
| 接口： | 總線 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 封裝/外殼： | 504-LBGA |
| 供應(yīng)商設(shè)備封裝： | 504-TBGA（35x35） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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XRT94L31
17
REV. 1.0.1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
E2
TXA_ALARM
O
CMOS
Transmit STS-3/STM-1 Telecom Bus - Alarm Indicator Output sig-
nal:
This output pin pulses "High", coincdent to the instant that the Transmit
STS-3/STM-1 Telecom Bus outputs a byte (via the TxA_D[7:0] output
pins) that pertains to any that STS-1 or STS-3c signal is carrying the
AIS-P indicator.
This output pin is "Low" for all other conditions.
NOTE:
This output pin is only active if the Transmit STS-3/STM-1
Telecom Bus Interface is enabled and has been configured to
operate in the Re-Phase OFF Mode.
H3
TXA_DP
O
CMOS
Transmit STS-3/STM-1 Telecom Bus - Parity Output pin:
This output pin can be configured to function as one of the following.To
reflect either the EVEN or ODD parity value of the bits which are cur-
rently being output via the TXA_D[7:0] output pins.
To reflect either the EVEN or ODD parity value of the bits which are cur-
rently being output via the TXA_D[7:0] output pins and the states of the
TXA_PL and TXA_C1J1 output pins.
NOTE: Any one of these configuration selections can be made by writing
the appropriate value into the Telecom Bus Control Register
(Address Location = 0x0137).
G4
TxSBFP
I
TTL
Transmit STS-3/STM-1 Frame Alignment Sync Input:
The Transmit STS-3 TOH Processor Block can be configured to initiate
its generation of a new outbound STS-3/STM-1 frame based upon an
externally supplied 8kHz clock signal to this input pin. If this feature is
used, the Transmit STS-3/STM-1 Telecom Bus Interface will begin trans-
mitting the very first byte of given STS-3 or STM-1 frame, upon sensing
a rising edge (of the 8kHz signal) at this input pin.
NOTES:
1. If this input pin is connected to GND, then the Transmit STS-3
TOH Processor block will generate its outbound STS-3/STM-1
frames asynchronously, with respect to any input signal.
2. This input signal must be synchronized with the signal that is
supplied to the REFTTL input pin. Failure to insure this will
result in bit errors being generated within the outbound STS-3/
STM-1 signal.
3. The user must supply an 8kHz pulse (to this input pin) that has
a width of approximately 51.4412.8ns (one 19.44MHz clock
period). The user must not apply a 50% duty cycle 8kHz signal
to this input pin.
4. Register HRSYNC_DLY (Address Location: 0x0135) defines
the timing for TxSBFP input pin.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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