Advanced Notebook I/O for ISA or LPC Designs
Datasheet
Rev. 0.5 (03-24-05)
Page 168
SMSC SIO10N268
DATASHEET
Table 10.3 - CR00
FDC POWER/VALID CONFIGURATION CYCLE
TYPE: R/W
DEFAULT: 0x20 on VCC POR
Bit[3] = 0 on a Hard Reset
BIT NO.
BIT NAME
DESCRIPTION
0-2
Reserved
Read Only. A read returns 0
3
FDC Power
(
Note 10.6)
A high level on this bit, supplies power to the FDC. A low level on
this bit puts the FDC in low power mode (default).
4,5,6
Reserved
Read only. A read returns bit 5 as a 1 and bits 4 and 6 as a 0.
7
Valid
A high level on this software controlled bit can be used to indicate
that a valid configuration cycle has occurred. The control software
must take care to set this bit at the appropriate times. Set to zero
after power up. This bit has no effect on any other hardware in the
chip.
Note 10.6
Power Down bits disable the respective logical device and associated pins, however the power down bit
does not disable the selected address range for the logical device. To disable the host address registers
the logical device’s base address must be set below 100h. Devices that are powered down but still
reside at a valid I/O base address will participate in Plug-and-Play range checking.
10.4.2 CR01
CR01 can only be accessed in the configuration state and after the CSR has been initialized to 01H.
Table 10.4 – CR01
PP POWER/MODE/CR LOCK
TYPE: R/W
DEFAULT: 0x98 on VCC POR;
Bit[7] = 1 and Bit[2]=0 on HARD RESET
BIT NO.
BIT NAME
DESCRIPTION
0,1
Reserved
Read Only. A read returns “0”.
2
Parallel Port
Power (
Note
10.7, Note 10.8)
A high level on this bit, supplies power to the Parallel Port. A low
level on this bit puts the Parallel Port in low power mode (Default).
3
Parallel Port
Mode
Parallel Port Mode. A high level on this bit, sets the Parallel Port for
Printer Mode (Default). A low level on this bit enables the Extended
Parallel port modes. Refer to Bits 0 and 1 of CR4
4
Reserved
Read Only. A read returns “1”.
5,6
Reserved
Read Only. A read returns “0”.
7
Lock CRx
A high level on this bit enables the reading and writing of CR00 –
CR39 (Default). A low level on this bit disables the reading and
writing of CR00 – CR39. Note: once the Lock CRx bit is set to “0”,
this bit can only be set to “1” by a hard reset or power-up reset.
Note 10.7
Power Down bits disable the respective logical device and associated pins, however the power down bit
does not disable the selected address range for the logical device. To disable the host address registers
the logical device’s base address must be set below 100h. Devices that are powered down but still
reside at a valid I/O base address will participate in Plug-and-Play range checking.
Note 10.8
On a VCC POR and a Hard Reset the Parallel Port defaults to powered off. When the Parallel Port
Power bit is cleared the parallel port interrupt (PINT) located in the SMI_STS2 register at offset 0x09 is
set to ‘1’.