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參數(shù)資料
| 型號： | SIO10N268-NU |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | 14 X 14 MM, 1MM THICKNESS, GREEN, TQFP-128 |
| 文件頁數(shù)： | 193/251頁 |
| 文件大?。?/td> | 1384K |
| 代理商： | SIO10N268-NU |
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Advanced Notebook I/O for ISA or LPC Designs
Datasheet
Rev. 0.5 (03-24-05)
Page 46
SMSC SIO10N268
DATASHEET
I/O devices located on the X-Bus interface may be accessed by I/O transactions on the LPC interface.
Memory or Flash devices located on the X-Bus interface may be accessed by LPC Memory or Firmware
Hub (FWH) cycles via the LPC interface. See sections 8.3.4.3 Memory Read and Write Cycles on page 37
and 8.4 FWH Interface (LPC Mode Only) on page 40 for decoding FWH cycles.
NOTE:
Chip Select nXCS[0] can be disabled from going active for a memory access by settting the corresponding
enable bit to ‘0’, which is located in the X-Bus Chip Select 0 Register. Chip Selects nXCS1and nXCS2
can be disabled from going active for an I/O access by setting the corresponding disable bit to ‘1’, which is
located in the associated Base I/O Address x
Low Byte register. These bits allow each chip select to be
individually enabled or disabled for either memory or I/O transactions.
8.5.1
I/O Cycles
The X-bus interface allows the SIO10N268 - LPC MODE to interface to as many as 2 external components
that have an 8 bit data bus.
Devices located on nXCS1 and nXCS2 are accessable by LPC I/O
transactions. These devices may have their Base I/O Addresses located on 2, 4, or 16 byte boundaries
depending on the X-Bus mode of operation. (See section 10.5 Logical Device Base I/O Address and
Range on page 215 for valid Base I/O Addresses for the X-Bus interface.) The SIO10N268 - LPC MODE
performs 16-bit address qualification on the X-Bus base I/O addresses.
That is, the upper 4-bits,
bits[15:12], must be ‘0’.
The X-Bus interface offers three different modes of operation for I/O devices on both I/O chip selects
(nXCS1 and nXCS2). In Mode 1, a 10-bit compare is performed on address bits[11:2] and address
bits[1:0] are forwarded to XA1 and XA0 respectively. In Mode 2, an 8-bit compare is performed on address
bits[11:4] and address bits[3:0] are forwarded to XA3 to XA0 respectively. In Mode 3, a 10-bit address
compare is performed on address bits[11:3] and bits[1] and if address is valid and bit[0]=0 then address
bit[2] is forwarded to XA2 .
The chip select outputs are generated by logic that compares the LPC I/O address bits with the X-bus base
I/O address configuration registers. The mode of operation determines the number of valid address pins
that the X-bus interface provides, as well as the number of bits in the base I/O addresses. The mode is
chosen via bits[1:0] of the X-Bus I/O Select Configuration Register located at CR52.
The options for X-bus modes are as follows:
Mode 1: The X-bus base I/O address configuration registers contain address bits A11 through A8 and
A7 through A2, respectively. A1 and A0 pass directly through to XA1 and XA0, respectively. The chip
selects only become active (low) for the LPC bus cycle in which the address match occurs.
Mode 2: The X-bus base I/O address configuration registers contain address bits A11 through A8 and
A7 through A4, respectively. A3, A2, A1 and A0 pass directly through to XA3, XA2, XA1 and XA0,
respectively. The chip selects only become active (low) for the LPC bus cycle in which the address
match occurs.
Mode 3: The X-bus base I/O address configuration registers contain address bits A11 through A8, A7
though A3, and A1. A2 passes directly through to XA2. A2 is used to select between the registers at
base address offset 0 and offset of 4. This mode allows communication with up to three register pairs
at a programmable base address and fixed offset of +4, for example (60,64), (62,66), (68,6C). The
chip selects only become active (low) for the LPC bus cycle in which the address match occurs. A0
(address bit 0 from LPC bus) must be ‘0’ since registers may only be accessed on even-byte
boundaries. That is, only even addresses are valid since the part checks that bit A0 is 0.
Each X-bus chip select base address register has an associated “write protect” bit that can only be set
once, and is reset by VCC POR and PCI Reset (i.e., Hard Reset). When this bit is set, it prevents the base
address configuration registers (high byte and low byte) for each chip select from being written. This
security feature ensures that the base address and disable bit for each chip select can only be set by BIOS
and cannot be corrupted by any virus software.
This bit is part of the X-bus Low Address Byte
Configuration register.
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