
Advanced Notebook I/O for ISA or LPC Designs
Datasheet
SMSC SIO10N268
Page 35
Rev. 0.5 (03-24-05)
DATASHEET
8.3
LPC Interface (LPC Mode only)
LPC Mode is enabled if the LPC_ISA pin (pin 54) is left unconnected of if it is connected to ground.
The SIO10N268 communicates with the host over a Low Pin Count (LPC) interface. For a complete
description of the LPC interface, see the Intel Low Pin Count Specification, Rev 1.0. The following
sections define the LPC signals implemented, the cycles supported, and protocols implemented that are
specific to this device.
NOTE:
The LPC interface uses 3.3V signaling.
For electrical specifications see the Intel Low Pin Count
Specification, Rev 1.0 and the PCI Local Bus Specification, Rev 2.2.
8.3.1
LPC Interface Signal Definition
The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI
33MHz electrical signal characteristics.
Table 8.2 – LPC Bus Interface Signals
SIGNAL NAME
TYPE
DESCRIPTION
LAD[3:0]
I/O
LPC address/data bus. Multiplexed command, address and data bus.
LFRAME#
Input
Frame signal. Indicates start of new cycle and termination of broken cycle
PCI_RESET#
Input
PCI Reset. Used as LPC Interface Reset.
LDRQ#
Output
Encoded DMA/Bus Master request for the LPC interface.
IO_PME#
OD
Power Mgt Event signal. Allows the SIO10N268 to request wakeup.
LPCPD#
Input
Powerdown Signal. Indicates that the SIO10N268 should prepare for power to be shut
on the LPC interface.
PCI_CLK
Input
PCI Clock.
CLKRUN#
I/OD
Clock Run. Allows the SIO10N268 to request the stopped PCI_CLK be started.
IO_SMI#
OD
System Mgt Interrupt signal. Allows the SIO10N268 to notify the host system that an
event has occurred.
Note 8.2
The IO_PME#, IO_SMI#, and PCI_CLK signals are considered part of the host interface. They are
available in both LPC Mode and ISA Mode.
8.3.2
LPC Cycles
The following cycle types are supported by the LPC protocol.
Table 8.3 – LPC Cycle Types
CYCLE TYPE (Note 8.3)
TRANSFER SIZE
I/O Write
1 Byte
I/O Read
1 Byte
DMA Write
1 Byte
DMA Read
1 Byte
Memory Read
1 Byte (Note 8.4, Note 8.5)
Memory Write
1 Byte (Note 8.4, Note 8.5)
Note 8.3
The SIO10N268 ignores cycles that it does not support.
Note 8.4
LPC memory is only supported within the FWH ranges specified in section 8.4.2 FWH and LPC Memory
Addressing on page 41.