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參數(shù)資料
| 型號(hào)： | SIO10N268-NU |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類(lèi)： | 外設(shè)及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | 14 X 14 MM, 1MM THICKNESS, GREEN, TQFP-128 |
| 文件頁(yè)數(shù)： | 40/251頁(yè) |
| 文件大?。?/td> | 1384K |
| 代理商： | SIO10N268-NU |
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Advanced Notebook I/O for ISA or LPC Designs
Datasheet
Rev. 0.5 (03-24-05)
Page 136
SMSC SIO10N268
DATASHEET
SMSC Application Note: Application Considerations When Using the Powerdown Feature of SMSC
Floppy Disk Controllers.
8.13.1.1 DSR From Powerdown
If DSR powerdown is used when the part is in auto powerdown, the DSR powerdown will override the auto
powerdown. However, when the part is awakened from DSR powerdown, the auto powerdown will once
again become effective.
8.13.1.2 Wake Up From Auto Powerdown
If the part enters the powerdown state through the auto powerdown mode, then the part can be awakened
by reset or by appropriate access to certain registers.
If a hardware or software reset is used then the part will go through the normal reset sequence. If the
access is through the selected registers, then the FDC resumes operation as though it was never in
powerdown. Besides activating the PCI_RESET# pin or one of the software reset bits in the DOR or DSR,
the following register accesses will wake up the part:
1) Enabling any one of the motor enable bits in the DOR register (reading the DOR does not awaken the
part).
2) A read from the MSR register.
3) A read or write to the Data register.
Once awake, the FDC will reinitiate the auto powerdown timer for 10 ms. The part will powerdown again
when all the powerdown conditions are satisfied.
8.13.1.3 Register Behavior
Table 8.51 illustrates the AT and PS/2 (including Model 30) configuration registers available and the type
of access permitted. In order to maintain software transparency, access to all the registers must be
maintained. As Table 8.51 shows, two sets of registers are distinguished based on whether their access
results in the part remaining in powerdown state or exiting it.
Access to all other registers is possible without awakening the part. These registers can be accessed
during powerdown without changing the status of the part. A read from these registers will reflect the true
status as shown in the register description in the FDC description. A write to the part will result in the part
retaining the data and subsequently reflecting it when the part awakens. Accessing the part during
powerdown may cause an increase in the power consumption by the part. The part will revert back to its
low power mode when the access has been completed.
8.13.1.4 Pin Behavior
The SIO10N268 is specifically designed for systems in which power conservation is a primary concern.
This makes the behavior of the pins during powerdown very important.
The pins of the SIO10N268 can be divided into two major categories: system interface and floppy disk
drive interface. The floppy disk drive pins are disabled so that no power will be drawn through the part as a
result of any voltage applied to the pin within the part's power supply range. Most of the system interface
pins are left active to monitor system accesses that may wake up the part.
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