
Advanced Notebook I/O for ISA or LPC Designs
Datasheet
Rev. 0.5 (03-24-05)
Page 146
SMSC SIO10N268
DATASHEET
PIN
NAME
POWER WELL
DEFAULT ON
VTR POR
DEFAULT ON
VCC POR
GPIO
PME/SMI
FUNCTION
40
GP36/nCTS3
VCC (Note 8.47)
GPIO Input
Programmable
PME
41
GP37/nDTR3
VCC (Note 8.47)
GPIO Input
Programmable
PME
42
GP40/nRI4
VCC (Note 8.48)
GPIO Input
Programmable
PME
43
GP41/nDCD4
VCC
GPIO Input
Programmable
-
44
GP42/nRXD4
VCC
GPIO Input
Programmable
-
45
GP43/nTXD4
VCC
GPIO Input
Programmable
-
46
GP44/nDSR4
VCC
GPIO Input
Programmable
-
47
GP45/nRTS4
VCC
GPIO Input
Programmable
-
48
GP46/nCTS4
VCC
GPIO Input
Programmable
-
50
GP47/nDTR4
VCC
GPIO Input
Programmable
-
51
GP12/IO_SMI#
VCC (Note 8.47)
GPIO Input
Programmable
IO_SMI#/
PME/SMI
53
GP13/IRQIN1/LED1
VCC (Note 8.47)
GPIO Input
Programmable
PME/SMI
55
XA20/GP16
VCC (Note 8.47)
X-Bus Address
bit[20] Output
Programmable
PME/SMI
56
XA19/GP17
VCC (Note 8.47)
X-Bus Address
bit[19] Output
Programmable
PME/SMI
60
GP20/IRRX2/IRQIN3
VCC (Note 8.47)
GPIO Input
Programmable
PME
61
GP21/IRTX2/WDT
VCC (Note 8.47)
GPIO Input
Programmable
PME
62
GP22/IRMODE/IRRX3/nX
CS2
VCC (Note 8.47)
GPIO Input
Programmable
PME
90
GP50/nRI2
VCC (Note 8.48)
GPIO Input
Programmable
PME
91
GP51/nDCD2
VCC
GPIO Input
Programmable
-
92
GP52/RXD2/IRRX
VCC
GPIO Input
Programmable
-
93
GP53/TXD2/IRTX
VCC
GPIO Input
Programmable
-
94
GP54/nDSR2
VCC
GPIO Input
Programmable
-
95
GP55/nRTS2
VCC
GPIO Input
Programmable
-
96
GP56/nCTS2
VCC
GPIO Input
Programmable
-
97
GP57/nDTR2 /MEMEN
VCC
GPIO Input
Programmable
-
Note 8.47
These pins have input buffers into the wakeup logic that are powered by VTR.
Note 8.48
This pin has an input buffer into the wakeup logic that are powered by VTR to support the nRI function.
8.16.2 Description
Each GPIO port has a 1-bit data register. GPIOs are controlled by GPIO control registers located in the
Configuration section. The data register for each GPIO port is represented as a bit in one of the 8-bit
GPIO DATA Registers, GP1 to GP5. The bits in these registers reflect the value of the associated GPIO
pin as follows. Pin is an input: The bit is the value of the GPIO pin. Pin is an output: The value written to
the bit goes to the GPIO pin. Latched on read and write. The GPIO data registers are located in the
Runtime Register block; see the Runtime Registers section. The GPIO ports with their alternate functions
and configuration state register addresses are listed in Table 8.56.