
Advanced Notebook I/O for ISA or LPC Designs
Datasheet
SMSC SIO10N268
Page 143
Rev. 0.5 (03-24-05)
DATASHEET
be generated on the Serial IRQ stream. The state of the GPIO pins will be reflected on the serial IRQ
stream. The IRQ selection bits should be ‘0000’ in the IRQ routing registers when GPIO functions are
used. These IRQ selection bits default to ‘0000’ on VCC POR.
8.15
PCI CLKRUN Support
8.15.1 Overview
The SIO10N268 supports the PCI CLKRUN# signal. CLKRUN# is used to indicate the PCI clock status as
well as to request that a stopped clock be started. The SIO10N268 CLKRUN# signal is on pin number 28.
See Figure 8.9 for an example of a typical system implementation using CLKRUN#.
If the SIO10N268 SIRQ_CLKRUN_EN signal is disabled, it will disable the CLKRUN# support related to
LDRQ# in addition to disabling the SER_IRQ and the CLKRUN# associated with SER_IRQ.
CLKRUN# is an open drain output and an input. Refer to the PCI Mobile Design Guide Rev 1.0 for a
description of the CLKRUN# function.
8.15.2 CLKRUN# for Serial IRQ
The SIO10N268 supports the PCI CLKRUN# signal for the Serial IRQs. If an SIO interrupt occurs while
the PCI clock is stopped, CLKRUN# is asserted before the serial interrupt signal is driven active.
See section 8.15.4 Using CLKRUN# below for more details.
8.15.3 CLKRUN# for LDRQ#
CLKRUN# support is also provided in the SIO10N268 for the LDRQ# signal. If a device requests DMA
service while the PCI clock is stopped, CLKRUN# is asserted to restart the PCI clock. This is required to
drive the LDRQ# signal active.
See section 8.15.4 Using CLKRUN# below for more details.
8.15.4 Using CLKRUN#
If CLKRUN# is sampled “high”, the PCI clock is stopped or stopping. If CLKRUN# is sampled “l(fā)ow”, the
PCI clock is starting or started (running). If a device in the SIO10N268 asserts or de-asserts an interrupt
or asserts a DMA request, and CLKRUN# is sampled “high”, the SIO10N268 requests the restoration of
the clock by asserting the CLKRUN# signal asynchronously (Table 8.54).
The SIO10N268 holds
CLKRUN# low until it detects two rising edges of the clock. After the second clock edge, the SIO10N268
disables the open drain driver (Figure 8.10).
The SIO10N268 will not assert CLKRUN# under any conditions if SIRQ_CLKRUN_EN is inactive (“0”).
The SIRQ_CLKRUN_EN bit is D7 in CR29.
The SIO10N268 will not assert CLKRUN# if it is already driven low by the central resource; i.e., the PCI
CLOCK GENERATOR in Figure 8.9. The SIO10N268 will not assert CLKRUN# unless the line has been
deasserted for two successive clocks; i.e., before the clock was stopped (Figure 8.10).