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參數(shù)資料
| 型號(hào)： | SIO10N268-NU |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類(lèi)： | 外設(shè)及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | 14 X 14 MM, 1MM THICKNESS, GREEN, TQFP-128 |
| 文件頁(yè)數(shù)： | 199/251頁(yè) |
| 文件大小： | 1384K |
| 代理商： | SIO10N268-NU |
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Advanced Notebook I/O for ISA or LPC Designs
Datasheet
SMSC SIO10N268
Page 51
Rev. 0.5 (03-24-05)
DATASHEET
NAME
SYMBOL
DESCRIPTION
PCI Clock
PCI_CLK
33MHz PCI clock input, used with the SIRQ and the CLKRUN# pins to serially
transfer SIO10N268 interrupts to the host.
Note: If serial IRQs are not supported then the PCI Clock input may be
connected to the PCI clock or 14.318MHz clock source.
ISA Reset Drive
RESET_DRV
This active high signal resets the chip and must be valid for 500ns minimum.
The effect on the internal registers is described in the appropriate section. The
configuration registers are not affected by this reset.
I/O Channel Ready
(Note 8.7)
IOCHRDY
This pin is pulled low to extend the read/write command. IOCHRDY can be used
by the IRCC and by the Parallel Port in EPP mode.
Power Management
Event
IO_PME#
Power Mgt Event signal. Allows the SIO10N268 to request wakeup.
System Management
Event
IO_SMI#
System Mgt Interrupt signal. Allows the SIO10N268 to notify the host system
that an event has occurred.
Note 8.7
An external pull-up must be provided for IOCHRDY.
The SER_IRQ, PCI_CLK, IO_PME#, and IO_SMI# signals are considered part of the host interface. They
are available in both LPC Mode and ISA Mode.
8.6.1
AEN signal
The AEN signal is used to indicate that a DMA operation is active on the host bus. It is used to prevent I/O
devices from responding to DMA transactions. Not all devices that provide an ISA interface support this
feature. For example, the 440MX chipset does not supply an AEN signal, instead it drives the address bus
to 0000h during a DMA I/O cycle to indicate a DMA transaction is occuring. The SIO10N268 has
implemented two modes of operation that are selectable via the AEN control bit located in the Clock/AEN
Control Register located at offset CR1E. This bit is implemented as shown.
bit[1] AEN Control
1) If the AEN Control bit is set to ‘0’ the internal AEN signal will be asserted if the AEN pin is high OR if
SA[0:15]=0000h (default).
2) If the AEN Control bit is set to ‘1’ the internal AEN signal will asserted only when the AEN pin is high.
NOTE:
System designers using the 440MX chipset should ground the AEN pin to prevent the AEN pin from
floating, thereby creating false DMA cycles.
The SIO10N268 only responds to I/O addresses above 100h.
8.7
Floppy Disk Controller
The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy
disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write
Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B
core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow
protection.
The FDC is compatible to the 82077AA using SMSC's proprietary floppy disk controller core.
The SIO10N268 supports one floppy disk drive directly through the FDC interface pins and two floppy disk
drives the FDC interface on the parallel port pins. It can also be configured to support on drive on the FDC
interface pins and one drive on the parallel port pins.
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相關(guān)代理商/技術(shù)參數(shù) |
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