
Advanced Notebook I/O for ISA or LPC Designs
Datasheet
SMSC SIO10N268
Page 97
Rev. 0.5 (03-24-05)
DATASHEET
8.8.1.7
Modem Control Register (MCR)
Address Offset = 4H, DLAB = X, READ/WRITE
This 8 bit register controls the interface with the MODEM or data set (or device emulating a MODEM). The
contents of the MODEM control register are described below.
Bit 0
This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic "1", the nDTR output is
forced to a logic "0". When bit 0 is a logic "0", the nDTR output is forced to a logic "1".
Bit 1
This bit controls the Request To Send (nRTS) output. Bit 1 affects the nRTS output in a manner identical to
that described above for bit 0.
Bit 2
This bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read or written
by the CPU.
Bit 3
Output 2 (OUT2). This bit is used to enable an UART interrupt. When OUT2 is a logic "0", the serial port
interrupt output is forced to a high impedance state - disabled. When OUT2 is a logic "1", the serial port
interrupt outputs are enabled.
Bit 4
This bit provides the loopback feature for diagnostic testing of the Serial Port. When bit 4 is set to logic "1",
the following occur:
1) The TXD is set to the Marking State(logic "1").
2) The receiver Serial Input (RXD) is disconnected.
3) The output of the Transmitter Shift Register is "looped back" into the Receiver Shift Register input.
4) All MODEM Control inputs (nCTS, nDSR, nRI and nDCD) are disconnected.
5) The four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2) are internally connected to the
four MODEM Control inputs (nDSR, nCTS, RI, DCD).
6) The Modem Control output pins are forced inactive high.
7) Data that is transmitted is immediately received.
This feature allows the processor to verify the transmit and receive data paths of the Serial Port. In the
diagnostic mode, the receiver and the transmitter interrupts are fully operational. The MODEM Control
Interrupts are also operational but the interrupts' sources are now the lower four bits of the MODEM Control
Register instead of the MODEM Control inputs. The interrupts are still controlled by the Interrupt Enable
Register.
Bits 5 through 7