
Advanced Notebook I/O for ISA or LPC Designs
Datasheet
Rev. 0.5 (03-24-05)
Page 10
SMSC SIO10N268
DATASHEET
LIST OF TABLES
Table 3.1 - SIO10N268 LPC Mode ..............................................................................................................................16
Table 3.2 - SIO10N268 ISA Mode................................................................................................................................17
Table 4.1 - Pin Functions .............................................................................................................................................18
Table 8.1 - Super I/O Block Addresses ........................................................................................................................34
Table 8.2 – LPC Bus Interface Signals ........................................................................................................................35
Table 8.3 – LPC Cycle Types.......................................................................................................................................35
Table 8.4
Number of Long Syncs Inserted for Memory Cycles .................................................................................39
Table 8.5 - FWH Strapping Options .............................................................................................................................40
Table 8.6 - Description of ISA Signals..........................................................................................................................50
Table 8.7 – Status, Data and Control Registers ...........................................................................................................52
Table 8.8 - Internal 2 Drive Decode (Normal)...............................................................................................................57
Table 8.9 - Internal 2 Drive Decode (Drives 0 and 1 Swapped) ...................................................................................57
Table 8.10 - Tape Select Bits.......................................................................................................................................57
Table 8.11 - Drive Type ID ...........................................................................................................................................58
Table 8.12 - Precompensation Delays .........................................................................................................................59
Table 8.13 - Data Rates ...............................................................................................................................................59
Table 8.14 - DRVDEN Mapping0 .................................................................................................................................60
Table 8.15 – Default Precompensation Delays ............................................................................................................60
Table 8.16 - FIFO Service Delay..................................................................................................................................61
Table 8.17 - Status Register 0......................................................................................................................................64
Table 8.18 - Status Register 1......................................................................................................................................65
Table 8.19 - Status Register 2......................................................................................................................................65
Table 8.20 - Status Register 3......................................................................................................................................66
Table 8.21 - Description of Command Symbols ...........................................................................................................69
Table 8.22 - Instruction Set ..........................................................................................................................................71
Table 8.23 - Sector Sizes.............................................................................................................................................79
Table 8.24 - Effects of MT and N Bits............................................................................................................................80
Table 8.25 - Skip Bit vs Read Data command..............................................................................................................80
Table 8.26 - Skip Bit vs. Read Deleted Data Command...............................................................................................81
Table 8.27 - Result Phase Table..................................................................................................................................81
Table 8.28 - Verify Command Result Phase Table ......................................................................................................83
Table 8.29 - Typical Values for Formatting...................................................................................................................84
Table 8.30 - Interrupt Identification................................................................................................................................86
Table 8.31 - Drive Control Delays (ms) ........................................................................................................................87
Table 8.32 - Effects of WGATE and GAP Bits .............................................................................................................90
Table 8.33 - Addressing the Serial Port .......................................................................................................................91
Table 8.34 - Interrupt Control Table ..............................................................................................................................95
Table 8.35 - Baud Rates ............................................................................................................................................102
Table 8.36 - Reset Function Table ..............................................................................................................................102
Table 8.37 - Register Summary for an Individual UART Channel ..............................................................................106
Table 8.38 - FIR Transceiver Module-Type Select.....................................................................................................110
Table 8.39 - IR Rx Data Pin Selection........................................................................................................................110
Table 8.40 - Parallel Port Connector ...........................................................................................................................112
Table 8.41 - EPP Pin Descriptions ..............................................................................................................................119
Table 8.42 - ECP Pin Descriptions..............................................................................................................................121
Table 8.43 - ECP Register Definitions .........................................................................................................................122
Table 8.44 - Mode Descriptions ..................................................................................................................................122
Table 8.45 - Extended Control Register ......................................................................................................................127
Table 8.46 – Extended Control Register (continued)..................................................................................................128
Table 8.47 - Extended Control Register (continued) ..................................................................................................128
Table 8.48 - Forward Channel Commands (HostAck Low), .......................................................................................129
Table 8.49 - Modified Parallel Port FDD Control ........................................................................................................133
Table 8.50 – FDC Parallel Port Pins ..........................................................................................................................133
Table 8.51 - PC/AT and PS/2 Available Registers .....................................................................................................137
Table 8.52 - State of Floppy Disk Drive Interface Pins in Powerdown........................................................................137
Table 8.53 - SER_IRQ Sampling Periods ..................................................................................................................140
Table 8.54 - SIO10N268 CLKRUN# Function ............................................................................................................144