參數(shù)資料
型號: SIO10N268-NU
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 外設及接口
英文描述: MULTIFUNCTION PERIPHERAL, PQFP128
封裝: 14 X 14 MM, 1MM THICKNESS, GREEN, TQFP-128
文件頁數(shù): 36/251頁
文件大?。?/td> 1384K
代理商: SIO10N268-NU
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Advanced Notebook I/O for ISA or LPC Designs
Datasheet
Rev. 0.5 (03-24-05)
Page 132
SMSC SIO10N268
DATASHEET
readIntrThreshold =(16-<threshold>) data bytes in FIFO
An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or equal
to (16-<threshold>). (If the threshold = 12, then the interrupt is set whenever there are 4-16 bytes in the
FIFO). The host must respond to the request by reading data from the FIFO. This process is repeated
until the last byte is transferred out of the FIFO. If at this time the FIFO is full, it can be completely emptied
in a single burst, otherwise a minimum of (16-<threshold>) bytes may be read from the FIFO in a single
burst.
8.10.7.14 Programmed I/O - Transfers from the Host to the FIFO
In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more
bytes free in the FIFO. At this time if the FIFO is empty it can be filled with a single burst before the empty
bit needs to be re-read. Otherwise it may be filled with writeIntrThreshold bytes.
writeIntrThreshold =
(16-<threshold>) free bytes in FIFO
An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is less than or equal to
<threshold>. (If the threshold = 12, then the interrupt is set whenever there are 12 or less bytes of data in
the FIFO.) The host must respond to the request by writing data to the FIFO. If at this time the FIFO is
empty, it can be completely filled in a single burst, otherwise a minimum of (16-<threshold>) bytes may be
written to the FIFO in a single burst. This process is repeated until the last byte is transferred into the
FIFO.
8.10.8 Parallel Port Floppy Disk Controller
The Floppy Disk Control signals are available optionally on the parallel port pins. When this mode is
selected, the parallel port is not available. There are two modes of operation, PPFD1 and PPFD2. These
modes can be selected in the Parallel and Serial Extended Setup Register (CR04). PPFD1 has only drive
1 on the parallel port pins; PPFD2 has drive 0 and 1 on the parallel port pins. See the Configuration
section for description of the register. The FDC_PP pin can be used to switch the parallel port pins
between the FDC and the parallel port functions. See the following sub-section.
The following parallel port pins are read as follows by a read of the parallel port register:
1) Data Register (read) = last Data Register (write)
2) Control Register read as "cable not connected" STROBE, AUTOFD and SLC = 0 and nINIT =1
3) Status Register reads: nBUSY = 0, PE = 0, SLCT = 0, nACK = 1, nERR = 1
The following FDC pins are all in the high impedence state when the PPFDC is actually selected by the
drive select register:
1) nWDATA, DENSEL, nHDSEL, nWGATE, nDIR, nSTEP, nDS1, nDS0, nMTR0, nMTR1.
2) If PPFDx is selected, then the parallel port can not be used as a parallel port until "Normal" mode is
selected.
The FDC signals are muxed onto the Parallel Port pins as shown in Table 8.50.
For ACPI compliance the FDD pins that are multiplexed onto the Parallel Port function independently of the
state of the Parallel Port controller. For example, if the FDC is enabled onto the Parallel Port the
multiplexed FDD interface functions normally regardless of the Parallel Port Power control, CR01.2.
Table 8.49 illustrates this functionality.
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