
Advanced Notebook I/O for ISA or LPC Designs
Datasheet
SMSC SIO10N268
Page 111
Rev. 0.5 (03-24-05)
DATASHEET
8.9.5
IR Transmit Pins
The IR transmit signal may be brought out onto the GP53/TXD2/IRTX pin or the GP21/IRTX2/WDT pin.
These pins, which are not powered by VTR, function as described below.
The following defines the acceptable states for the GP53/TXD2/IRTX output pin following a VCC POR or
Hard Reset.
If VCC=0V the GP53/TXD2/IRTX pin will be tristate.
If VCC>2.4V and TXD2/IRTX functions are selected the following states are possible.
- If UART2 Power bit = 0 OR bits[7:6] IR Output Mux EQUAL ‘11’ at offset CR0A the output will be
tristate
- If UART2 Power bit = 1 AND bits[7:6] IR Output Mux EQUAL ‘00’ at offset CR0A AND the transmit
buffer is empty the output will be set to the inactive state.
- If UART2 Power bit = 1 AND bits[7:6] IR Output Mux EQUAL ‘00’ at offset CR0A AND the transmit
buffer has data and is ready to transmit the output will reflect the state of the data being
transmitted.
- If UART2 Power bit = 1 AND bits[7:6] IR Output Mux EQUAL ‘01’ at offset CR0A the output will be
low.
If VCC>2.4V and GP53 function is selected the pin will reflect the current state of GP53.
The following defines the acceptable states for the GP21/IRTX2/WDT output pin following a VCC POR or
Hard Reset.
If VCC=0V the GP21/IRTX2/WDT pin will be tristate.
If VCC>2.4V and IRTX2 function is selected the following states are possible.
- If bits[7:6] IR Output Mux EQUAL ‘11’ at offset CR0A the output will be tristate
- If UART2 Power bit = 0 AND bits[7:6] IR Output Mux NOT EQUAL ‘11’ at offset CR0A the output
will be low.
- If UART2 Power bit = 1 AND bits[7:6] IR Output Mux EQUAL ‘01’ at offset CR0A AND the transmit
buffer is empty the output will be set to the inactive state.
- If UART2 Power bit = 1 AND bits[7:6] IR Output Mux EQUAL ‘01’ at offset CR0A AND the transmit
buffer has data and is ready to transmit the output will reflect the state of the data being
transmitted.
- If UART2 Power bit=1 AND bits[7:6] IR Output Mux EQUAL ‘00’ the output will be low.
If VCC>2.4V and GP21 function is selected the pin will reflect the current state of GP21.
If VCC>2.4 and WDT function is selected the pin will reflect the current state of the WDT.
NOTE:
The inactive state for GP53/TXD2/IRTX pin or GP21/IRTX2/WDT pin is determined by a combination of
the mode selected and the function enabled on the pin. If the TXD2/IRTX or IRTX2 functions are enabled
the inactive state is determined by the IR Output Mux bits located in CR0A ECP FIFO Threshold/IR MUX
register and the UART Mode register located at CR0C.
8.10
Parallel Port
The SIO10N268 incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type
bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port
(ECP) parallel port modes. Refer to the Configuration Registers for information on disabling, power down,
changing the base address of the parallel port, and selecting the mode of operation.
The SIO10N268 also provides a mode for support of the floppy disk controller on the parallel port.
The parallel port also incorporates SMSC's ChiProtect circuitry, which prevents possible damage to the
parallel port due to printer power-up.