
Advanced Notebook I/O for ISA or LPC Designs
Datasheet
SMSC SIO10N268
Page 3
Rev. 0.5 (03-24-05)
DATASHEET
TABLE OF CONTENTS
Chapter 1
General Description ........................................................................................................... 13
Chapter 2
Pin Layouts ......................................................................................................................... 14
2.1
LPC Mode ......................................................................................................................................... 14
2.2
ISA Mode........................................................................................................................................... 15
Chapter 3
Pin Configurations for SIO10N268 .................................................................................. 16
Chapter 4
Description of Pin Functions ............................................................................................. 18
4.1
Buffer Type Description..................................................................................................................... 28
4.2
Design Guidelines for Implemented Buffer Types ............................................................................ 28
Chapter 5
Block Diagram.................................................................................................................... 29
Chapter 6
3.3 Volt Operation / 5 Volt Tolerance .............................................................................. 30
Chapter 7
Power Functionality ........................................................................................................... 31
7.1
VCC Power........................................................................................................................................ 31
7.2
VTR Support...................................................................................................................................... 31
7.3
32.768 kHz Trickle Clock Input ......................................................................................................... 31
7.4
Internal PWRGOOD .......................................................................................................................... 32
7.5
Trickle Power Functionality ............................................................................................................... 32
7.6
Maximum Current Values.................................................................................................................. 33
7.7
Power Management Events (PME/SCI)............................................................................................ 33
Chapter 8
Functional Description....................................................................................................... 34
8.1
Super I/O Registers........................................................................................................................... 34
8.2
Host Processor Interface (LPC or ISA) ............................................................................................. 34
8.3
LPC Interface (LPC Mode only) ........................................................................................................ 35
8.3.1
LPC Interface Signal Definition ...............................................................................................................35
8.3.2
LPC Cycles .............................................................................................................................................35
8.3.3
LFRAME# Usage....................................................................................................................................36
8.3.4
Field Definitions ......................................................................................................................................36
8.3.4.1
I/O Read and Write Cycles ..............................................................................................................36
8.3.4.2
DMA Read and Write Cycles ...........................................................................................................36
8.3.4.3
Memory Read and Write Cycles ......................................................................................................37
8.3.5
Power Management................................................................................................................................37
8.3.5.1
CLOCKRUN Protocol ......................................................................................................................37
8.3.5.2
LPCPD Protocol ..............................................................................................................................37
8.3.5.3
SYNC Protocol ................................................................................................................................38
8.3.5.4
SYNC Timeout.................................................................................................................................38
8.3.5.5
SYNC Patterns and Maximum Number of SYNCS ..........................................................................38
8.3.5.6
SYNC Error Indication .....................................................................................................................38
8.3.5.7
Reset Policy.....................................................................................................................................39
8.3.6
LPC Transfers ........................................................................................................................................39
8.3.6.1
Wait State Requirements.................................................................................................................39
8.4
FWH Interface (LPC Mode Only) ...................................................................................................... 40
8.4.1
Enabling the FWH Interface....................................................................................................................40
8.4.1.1
MEMEN ...........................................................................................................................................40
8.4.1.2
FWHSEL .........................................................................................................................................40
8.4.2
FWH and LPC Memory Addressing........................................................................................................41
8.4.3
FWH Cycle Types...................................................................................................................................41
8.4.4
Field Definitions ......................................................................................................................................42
8.4.4.1
START.............................................................................................................................................42
8.4.4.2
IDSEL ..............................................................................................................................................42
8.4.4.3
MSIZE .............................................................................................................................................42
8.4.4.4
MADDR ...........................................................................................................................................42