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參數(shù)資料
| 型號(hào)： | SIO10N268-NU |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | 14 X 14 MM, 1MM THICKNESS, GREEN, TQFP-128 |
| 文件頁(yè)數(shù)： | 39/251頁(yè) |
| 文件大?。?/td> | 1384K |
| 代理商： | SIO10N268-NU |
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Advanced Notebook I/O for ISA or LPC Designs
Datasheet
SMSC SIO10N268
Page 135
Rev. 0.5 (03-24-05)
DATASHEET
8.12
LED Functionality
The SIO10N268 provides LED functionality on two pins:
GP13/IRQIN1/LED1
GP23/LED2/IRQIN2
The LED logic and supporting registers are powered by VTR. The LED1 pin is powered by VCC and the
LED2 pin is powered by VTR. These pins can be configured to turn an LED on and off and blink
independent of each other through the LED1 and LED2 runtime registers at offset 0x15 and 0x16, when the
device is powered by VCC. See section Chapter 9 Runtime Registers for a description of these registers.
The LED2 pin (GP23) is capable of controlling an LED while the device is under VTR power with VCC
removed. In order to control an LED while the part is under VTR power, the GPIO pin must have been
configured for the LED2 function while the device was powered by VCC.
NOTE:
The LED2 pin will not support the blink function under VTR power (VCC removed) if an external 32kHz
clock source is not connected.
NOTE:
LED1 and LED2 may be configured for either open drain or push-pull buffer type. In the case of open-
drain buffer type, the pin is capable of sinking current to control the LED. In the case of push-pull buffer
type the part will source current.
8.13
Power Management
Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART
2, UART 3, UART 4, and the parallel port. For each logical device, two types of power management are
provided: direct powerdown and auto powerdown.
8.13.1 FDC Power Management
Direct power management is controlled by Bit[3] in CR00. Refer to the Configuration section for more
information.
Auto Power Management is enabled by Bit[7] in CR07. When set, this bit allows FDC to enter powerdown
when all of the following conditions have been met:
1) The motor enable pins of register 3F2H are inactive (zero).
2) The part must be idle; MSR=80H and INT = 0 (INT may be high even if MSR = 80H due to polling
interrupts).
3) The head unload timer must have expired.
4) The Auto powerdown timer (10msec) must have timed out.
An internal timer is initiated as soon as the auto powerdown command is enabled. The part is then
powered down when all the conditions are met.
Disabling the auto powerdown mode cancels the timer and holds the FDC block out of auto powerdown.
NOTE:
At least 8us delay should be added when exiting FDC Auto Powerdown mode. If the operating
environment is such that this delay cannot be guaranteed, the auto powerdown mode should not
be used and Direct powerdown mode should be used instead. The Direct powerdown mode
requires at least 8us delay at 250K bits/sec configuration and 4us delay at 500K bits/sec. The delay
should be added so that the internal microcontroller can prepare itself to accept commands. See
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