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參數(shù)資料
| 型號(hào)： | SK12439PJT |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 800 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 1/18頁(yè) |
| 文件大?。?/td> | 233K |
| 代理商： | SK12439PJT |
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HIGH-PER.ORMANCE PRODUCTS
1
www.semtech.com
Revision 1/February 9, 2001
SK12439
High .requency PLL
Clock Synthesizer
Description
.eatures
ADVANCED
The SK12439 is a general purpose synthesized clock
source. Its internal VCO will operate over a range of
frequencies from 400 to 800 MHz. The differential PECL
output can be configured to be the VCO frequency divided
by 1, 2, 4, or 8. With the output configured to divide the
VCO frequency by 1, and with a 16.66 MHz external quartz
crystal used to provide the reference frequency, the output
frequency can be specified in 16.66 MHz steps. The
output frequency is configured using a parallel or serial
interface.
The internal oscillator uses the external quartz crystal as
the basis of its frequency reference. The output of the
reference oscillator is divided by 2 before being sent to
the phase detector.
With a 16.66 MHz crystal, this
provides a reference frequency of 8.33 MHz. Although
this datasheet illustrates functionality only for a 16 MHz
and 16.66 MHz crystal, any crystal in the 10–20 MHz
range can be used. In addition to the crystal, an LVCMOS
input can also be used as the PLL reference. The reference
is selected via the XTAL_SEL input pin.
The VCO within the PLL operates over a range of 400 to
800 MHz. Its output is scaled by a divider that is configured
by either the serial or parallel interfaces. The output of
this loop divider is also applied to the phase detector.
The phase detector and loop filter attempt to force the
VCO output frequency to be 2 X M times the reference
frequency by adjusting the VCO control voltage. Note that
for some values of M (either too high or too low) the PLL
will not achieve loop lock.
The output of the VCO is also passed through an output
divider before being sent to the PECL output driver. This
output divider is configured through either the serial or
the parallel interfaces and can provide one of four division
ratios (1, 2, 4, or 8). This divider extends performance of
the part while providing a 50% duty cycle.
The output driver is driven differentially from the output
divider and is capable of driving a pair of transmission
lines terminated in 50
to VCC – 2.0V.
The configuration logic has two sections:
serial and
parallel. The parallel interface uses the values at the
M[6:0] and N[1:0] inputs to configure the internal
counters. Normally, on system reset, the P_LOAD input is
held LOW until sometime after power becomes valid. On
the LOW-to-HIGH transition of P_LOAD, the parallel inputs
are captured. The parallel interface has priority over the
serial interface. Internal pull-up resistors are provided on
the M[6:0] and N[1:0] inputs to reduce component count
in the application of the chip.
The serial interface centers on a 12-bit shift register. The
shift register shifts once per rising edge of the S_CLOCK
input. The serial input S_DATA must meet set-up and
hold timing as specified in the AC Characteristics section
of this document. The configuration latches will capture
the value of the shift register on the HIGH-to-LOW edge of
the S_LOAD input. See the programming section for more
information.
The TEST output reflects various internal node values and
is controlled by the T[2:0] bits in the serial data stream.
See the programming section for more information.
The PWR_DOWN pin, when asserted, will synchronously
divide the FOUT by 16. The power down sequence is
clocked by the PLL reference clock, thereby causing the
frequency reduction to happen relatively slowly. Upon de-
assertion of the PWR_DOWN, pin the FOUT input will step
back up to its programmed frequency in four discrete
increments.
50 to 800 MHz Differential PECL Outputs
±25 ps Typical Peak-to-Peak Output Jitter
Minimal Frequency Over-Shoot
Synthesized Architecture
Serial 3-Wire Interface
Parallel Interface for Power-Up
Quartz Crystal Interface
Fully Compatible with MC12439
Available in 28-Lead PLCC Package
Operates from 3.3V or 5.0V Power Supply
ESD Protection of >4000V
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相關(guān)代理商/技術(shù)參數(shù) |
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| SK125 | 制造商:Thomas & Betts 功能描述: |
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| SK12516 | 制造商:Cooper Wiring Devices 功能描述: |
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