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| 型號(hào)： | SIO10N268-NU |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類(lèi)： | 外設(shè)及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | 14 X 14 MM, 1MM THICKNESS, GREEN, TQFP-128 |
| 文件頁(yè)數(shù)： | 173/251頁(yè) |
| 文件大?。?/td> | 1384K |
| 代理商： | SIO10N268-NU |
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Advanced Notebook I/O for ISA or LPC Designs
Datasheet
Rev. 0.5 (03-24-05)
Page 28
SMSC SIO10N268
DATASHEET
4.1
Buffer Type Description
I
Input TTL Compatible.
IS
Input with Schmitt Trigger.
IPD
Input with 30uA Integrated Pull-Down
O6
Output, 6mA sink, 3mA source.
O8
Output, 8mA sink, 4mA source.
OD8
Open Drain Output, 8mA sink.
IO8
Input/Output, 8mA sink, 4mA source.
O12
Output, 12mA sink, 6mA source.
OD12
Open Drain Output, 12mA sink.
IO12
Input/Output, 12mA sink, 6mA source.
OD14
Open Drain Output, 14mA sink.
OP14
Output, 14mA sink, 14mA source.
IOP14
Input/Output, 14mA sink, 14mA source. Backdrive protected.
PCI_I
Input. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 4.20)
PCI_O
Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 4.20)
PCI_OD
Open Drain Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 4.20)
PCI_IO
Input/Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 4.20)
PCI_ICLK
Clock Input. These pins meet the PCI 3.3V AC and DC Characteristics and timing. (Note 4.21)
Note 4.20
See the PCI Local Bus Specification, Revision 2.1, Section 4.2.2.
Note 4.21
See the PCI Local Bus Specification, Revision 2.1, Section 4.2.2. and 4.2.3.
4.2
Design Guidelines for Implemented Buffer Types
The characteristics of the I/O buffers implemented in this device are defined in section 11.2 DC Electrical
Characteristics on page 218. Care should be taken to ensure that external devices maintain acceptable
voltage levels on all inputs and open drain outputs. It is not advisable to allow input buffers to float or
remain in an indeterminate state.
NOTE:
It is important not to cross power domains when attaching pull-ups to pins. Pins that are located on the
VCC power well must be pulled either to ground or to VCC. This includes GPIO pins with wakeup capability
that are located on the VCC power well (see Table 4.1 - Pin Functions on page 18).
Pins that are located on the VTR power well must be pulled either to ground or to VTR.
The following is a list of design guidelines to help identify which pins require external pull-up/pull-down
resistors:
1) Input buffers that are of type I or IS must be driven to a logic high or a logic low when power is applied
to the buffer. If the external device controlling the input buffer tristates while power is applied to the
buffer, an external pull-up/pull-down resistor should be added to prevent the pin from floating.
2) All output pins that are implemented as open drain outputs, must be pulled through an external
resistor to the proper VCC or VTR power plane.
3) All GPIO registers default to a GPIO input on a VTR POR. On a cold boot, a VCC POR will implement
these pins as GPIO inputs. It is suggested that these pins are pulled to their inactive state (either to
the proper VCC or VTR power plane or ground) depending on the function being implemented on the
pin.
4) Bi-directional buffers that change direction as part of their functionality require either pull-ups or pull-
downs to prevent the input buffer from floating when the bus is tristated. The SIO10N268 has bi-
directional data busses that require external resistors pulled to a logic high or a logic low. They are
the parallel data pins (PD[0:7]), the X-Bus data pins (XD[0:7]) – LPC Mode only, and ISA data pins
(SD[0:7]) – ISA Mode only)
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