
Advanced Notebook I/O for ISA or LPC Designs
Datasheet
Rev. 0.5 (03-24-05)
Page 32
SMSC SIO10N268
DATASHEET
The following functions will not work under VTR power (VCC removed) if the external 32kHz clock is not
connected. These functions will work under VCC power even if the external 32kHz clock is not connected.
LED blink
WDT
7.4
Internal PWRGOOD
An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the
host interface as VCC cycles on and off. When the internal PWRGOOD signal is “1” (active), VCC > 2.3V
(nominal), and the SIO10N268 host interface is active. When the internal PWRGOOD signal is “0”
(inactive), VCC ≤ 2.3V (nominal), and the SIO10N268 host interface is inactive; that is, LPC bus reads and
writes will not be decoded.
The SIO10N268 device pins IO_PME#, nRI1, nRI2, nRI3, nRI4, and most GPIOs (as input) are part of the
PME interface and remain active when the internal PWRGOOD signal has gone inactive, provided VTR is
powered. See Trickle Power Functionality section.
7.5
Trickle Power Functionality
When the SIO10N268 is running under VTR only, the PME wakeup events are active and (if enabled) able
to assert the IO_PME# pin active low. The following lists the wakeup events:
UART 1 Ring Indicator
UART 2 Ring Indicator
UART 3 Ring Indicator
UART 4 Ring Indicator
WDT
GPIOs for wakeup. See below.
The following requirements apply to all I/O pins that are specified to be 5 volt tolerant.
I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0),
these pins may only be configured as inputs. These pins have input buffers into the wakeup logic that
are powered by VTR.
I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0), are
powered by VTR. This means they will, at a minimum, source their specified current from VTR even
when VCC is present.
The GPIOs that are used for PME wakeup inputs are GP11-GP13, GP16-GP17, GP20-GP23, GP30-
GP37, GP40, and GP50. These GPIOs function as follows:
Buffers are powered by VCC, but in the absence of VCC they are backdrive protected (they do not
impose a load on any external VTR powered circuitry). They are wakeup compatible as inputs under
VTR power. These pins have input buffers into the wakeup logic that are powered by VTR.
All GPIOs listed above are for PME wakeup as a GPIO function (or alternate function).
See the Table in the GPIO section for more information.
The following list summarizes the blocks, registers and pins that are powered by VTR.
PME interface block
CLKI32
WDT block