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| 型號(hào)： | SIO10N268-NU |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | 14 X 14 MM, 1MM THICKNESS, GREEN, TQFP-128 |
| 文件頁數(shù)： | 198/251頁 |
| 文件大?。?/td> | 1384K |
| 代理商： | SIO10N268-NU |
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Advanced Notebook I/O for ISA or LPC Designs
Datasheet
Rev. 0.5 (03-24-05)
Page 50
SMSC SIO10N268
DATASHEET
The X-Bus supports flash speed selection by offering a programmable read/write pulse width (see section
12.4.3 X-Bus Memory Cycle Timing on page 230. The read/write pulse width is determined by the Pulse
Width Selection bits located in X-Bus Chip Select 0 Register at offset CR53. These bits allow the
read/write strobe to be held active for a minimum of 60, 90, 120, or 150 nsec.
The X-Bus Chips Select 0 Register offers a write protect bit. This bit affords the BIOS the ability to
program CR53 for a particular configuration, which cannot be altered until a VCC POR or Hard Reset.
NOTE:
To tristate the X-Bus for production line Flash update put the device in XNOR chain test mode.
8.6
ISA Interface (ISA Mode Only)
ISA Mode is enabled by pulling pin 54 (LPC_ISA) directly to VCC – a pull-up resistor should not be used.
The ISA interface is a standard AT (Advanced Technology) interface, that is compatible with the ISA
(Industry Standard Architecture) as documented by IEEE (IEEE P996 compatible). This interface supports
I/O and DMA transactions as defined by this defacto standard. In addition this interface has been modified
to have the option of supporting ISA devices that do not have an AEN output signal (Devices like the Intel
440MX chipset). The following sections define the signals on the ISA interface and the modifications made
to support special chipsets like the 440MX.
NOTE:
For ISA timing see section 12.5 Host Timing (ISA Mode Only) on page 232.
Table 8.6 - Description of ISA Signals
NAME
SYMBOL
DESCRIPTION
System Data Bus 0-7 SD0-SD7
The system data bus connection used by the host microprocessor to transmit
data to and from the chip. These pins are in a high-impedance state when not in
the output mode.
I/O Read
nIORD
This active low signal is issued by the host microprocessor to indicate an I/O
read operation.
I/O Write
nIOWR
This active low signal is issued by the host microprocessor to indicate an I/O
write operation.
Address Enable
AEN
Active high Address Enable indicates DMA operations on the host data bus.
Used internally to qualify appropriate address decodes. (See section 8.6.1 AEN
signal following table.)
System Address Bus
SA0-SA15
These host address bits determine the I/O address to be accessed during nIOR
and nIOW cycles. These bits are latched internally by the leading edge of nIOR
and nIOW. All internal address decodes use the full A0 to A15 address bits.
DMA Request
0, 1, 2, 3
DRQ_0
DRQ_1
DRQ_2
DRQ_3
These active high outputs are the DMA request for byte transfers of data
between the host and the chip. These signals are cleared on the last byte of the
data transfer by the nDACK signal going low (or by nIOR going low if nDACK
was already low as in demand mode).
nDMA
Acknowl-edge
0, 1, 2, 3
nDACK_0
nDACK_1
nDACK_2
nDACK_3
These are active low inputs acknowledging the request for a DMA transfer of
data between the host and the chip. These inputs enable the DMA read or write
internally.
Terminal Count
TC
This signal indicates that DMA data transfer is complete. TC is only accepted
when nDACK_x is low. In AT and PS/2 model 30 modes, TC is active high and
in PS/2 mode, TC is active low.
Serial IRQ
SER_IRQ
Serial IRQ pin used with the PCI_CLK pin to transfer SIO10N268 interrupts to
the host.
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