
Advanced Notebook I/O for ISA or LPC Designs
Datasheet
Rev. 0.5 (03-24-05)
Page 138
SMSC SIO10N268
DATASHEET
FDD PINS
STATE IN AUTO POWERDOWN
DRVDEN[0:1]
Tristated
8.13.2 UART Power Management
Direct power management is controlled by CR02. Refer to the Configuration section for more information.
Auto Power Management may be enabled by the UART1, UART2, UART3, or UART4 enable bits in CR07.
When set, these bits allow the following auto power management operations:
1) The transmitter enters auto powerdown when the transmit buffer and shift register are empty.
2) The receiver enters powerdown when the following conditions are all met:
a)
Receive FIFO is empty
b)
The receiver is waiting for a start bit.
NOTE:
While in powerdown the Ring Indicator interrupt is still valid and transitions when the RI input changes.
8.13.2.1 Exit Auto Powerdown
The transmitter exits powerdown on a write to the XMIT buffer. The receiver exits auto powerdown when
RXDx changes state.
8.13.3 Parallel Port
Direct power management is controlled by Bit[2] in CR01. Refer to the Configuration section for more
information.
Auto Power Management is enabled by Bit[4] in CR07. When set, this bit allows the ECP or EPP logical
parallel port blocks to be placed into powerdown when not being used.
The EPP logic is in powerdown under any of the following conditions:
1) EPP is not enabled in the configuration registers.
2) EPP is not selected through ecr while in ECP mode.
The ECP logic is in powerdown under any of the following conditions:
1) ECP is not enabled in the configuration registers.
2) SPP, PS/2 Parallel port or EPP mode is selected through ecr while in ECP mode.
8.13.3.1 Exit Auto Powerdown
The parallel port logic can change powerdown modes when the ECP mode is changed through the ecr
register or when the parallel port mode is changed through the configuration registers.
8.14
Serial IRQ
The SIO10N268 supports the serial interrupt to transmit interrupt information to the host system. The
serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0. The
PCI_CLK, SER_IRQ and nCLKRUN pins are used for this interface. The Serial IRQ/CLKRUN Enable bit
D7 in CR29 activates the serial interrupt interface.