Glossary of Terms and Abbreviations
Glossary-11
Register indirect with index addressing
. A form of addressing that speciTes
that the contents of two GPRs be added together to yield the target
address for the load or store.
Rename register
. Temporary buffers used by instructions that have Tnished
execution but have not completed.
Reservation
. The processor establishes a reservation on a
cache block
of
memory space when it executes an
lwarx
instruction to read a
memory semaphore into a GPR.
Reservation station
. A buffer between the dispatch and execute stages that
allows instructions to be dispatched even though the results of
instructions on which the dispatched instruction may depend are not
available.
Retirement
. Removal of the completed instruction from the CQ
RISC (reduced instruction set computing)
. An
architecture
characterized
by Txed-length instructions with nonoverlapping functionality and
by a separate set of load and store instructions that perform memory
accesses.
Secondary cache
. A cache memory that is typically larger and has a longer
access time than the primary cache. A secondary cache may be
shared by multiple devices. Also referred to as L2, or level-2, cache.
Sector
. A 32-byte cache block.
Set
(
v
). To write a nonzero value to a bit or bit Teld; the opposite of
clear
. The
term set may also be used to generally describe the updating of a
bit or bit Teld.
Set
(
n
). A subdivision of a
cache
. Cacheable data can be stored in a given
location in any one of the sets, typically corresponding to its lower-
order address bits. Because several memory locations can map to the
same location, cached data is typically placed in the set whose
cache
block
corresponding to that address was used least recently.
See
Set-
associative.
Set-associative
. Aspect of cache organization in which the cache space is
divided into sections, called
sets
. The cache controller associates a
particular main memory address with the contents of a particular set,
or region, within the cache.
S