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MPC7400 RISC Microprocessor Users Manual
60x/MPX Bus Protocol Signal Compatibility
Timing Comments
AssertionMust not occur before ARTRY for the current
transaction (if the address retry mechanism is to be used to prevent
invalid data from being used by the processor); otherwise, assertion
may occur at any time during a data tenure. The system can withhold
assertion of TA to indicate that the MPC7400 should insert wait
states to extend the duration of the data beat.
NegationMust occur after the bus clock cycle of the Tnal (or only)
data beat of the transfer. For a burst transfer, the system can assert TA
for one bus clock cycle and then negate it to advance the burst
transfer to the next beat and insert wait states during the next beat.
8.2.8.2 Transfer Error Acknowledge (TEA)
Input
Following are the state meaning and timing comments for the TEA signal.
State Meaning
AssertedIndicates that a bus error occurred. Causes a machine
check exception (and possibly causes the processor to enter
checkstop state if machine check enable bit is cleared
(MSR[ME] = 0)). For more information, see Section 4.6.2.2,
òCheckstop State (MSR[ME] = 0).ó Assertion terminates the current
transaction; that is, assertion of TA is ignored. The assertion of TEA
causes the negation/high impedance of DBB in the next clock cycle.
However, data entering the GPR or the cache is not invalidated.
NegatedIndicates that no bus error was detected.
Timing Comments
AssertionMay be asserted while DBB is asserted, up to and
including the cycle of the Tnal TA. TEA should be asserted for one
cycle only.
NegationTEA must be negated one cycle after it is asserted.
8.3 60x/MPX Bus Protocol Signal Compatibility
The MPX bus mode protocol deTnes several new signals not present in the 60x bus
protocol. Also, there are 60x signals not supported by the MPC7400. These signal
differences are summarized in Table 8-6. Note that a few 60x signals have expanded or
modiTed functionality in the MPX bus mode.