2-64
MPC7400 RISC Microprocessor Users Manual
Instruction Set Summary
2.3.5.1 Processor Control InstructionsVEA
In addition to the move to condition register instructions (speciTed by the UISA), the VEA
deTnes the
mftb
instruction (user-level instruction) for reading the contents of the time base
register; see Chapter 3, òL1 and L2 Cache Operation,ó for more information. Table 2-48
shows the
mftb
instruction.
SimpliTed mnemonics are provided for the
mftb
instruction so it can be coded with the
TBR name as part of the mnemonic rather than requiring it to be coded as an operand. See
Appendix F, òSimpliTed Mnemonics,ó in
The Programming Environments Manual
for
simpliTed mnemonic examples and for simpliTed mnemonics for Move from Time Base
(
mftb
) and Move from Time Base Upper (
mftbu
), which are variants of the
mftb
instruction rather than of
mfspr
. The
mftb
instruction serves as both a basic and simpliTed
mnemonic. Assemblers recognize an
mftb
mnemonic with two operands as the basic form,
and an
mftb
mnemonic with one operand as the simpliTed form. Note that the MPC7400
ignores the extended opcode differences between
mftb
and
mfspr
by ignoring bit 25 and
treating both instructions identically.
Implementation Note
sIn the MPC7400, note the following:
¥
The MPC7400 allows user-mode read access to the time base counter through the
use of the Move from Time Base (
mftb
) and the Move from Time Base Upper
(
mftbu
) instructions. As a 32-bit PowerPC implementation, the MPC7400 can
access TBU and TBL separately only.
The time base counter is clocked at a frequency that is one-fourth that of the bus
clock. Counting is enabled by assertion of the time base enable (TBEN) input signal.
¥
2.3.5.2 Memory Synchronization InstructionsVEA
Memory synchronization instructions control the order in which memory operations are
completed with respect to asynchronous events, and the order in which memory operations
are seen by other processors or memory access mechanisms. See Chapter 3, òL1 and L2
Cache Operation,ó for more information about these instructions and about related aspects
of memory synchronization.
In addition to the
sync
instruction (speciTed by UISA), the VEA deTnes the Enforce
In-Order Execution of I/O
(
eieio
) and Instruction Synchronize (
isync
) instructions. The
number of cycles required to complete an
eieio
instruction depends on system parameters
and on the processor's state when the instruction is issued. As a result, frequent use of this
instruction can degrade performance.
Table 2-48. Move from Time Base Instruction
Name
Mnemonic
Syntax
Move from Time Base
mftb
r
D, TBR