Chapter 11. Performance Monitor
11-13
Event Selection
00011Number of TBL bit transitions from 0 to 1 of speciTed TBL bits. Bits
are speciTed through MMCR0[TBSEL]:
D 00 = TB[63] (TBL[31])
D 01 = TB[55] (TBL[23])
D 10 = TB[51] (TBL[19])
D 11 = TB[47] (TBL[15])
00100Number of instructions dispatched. 0, 1, or 2 per cycle
11.5.1 PMC1 Events
The event to be monitored can be chosen by setting MMCR0[19D31]. The selected events
are counted beginning when MMCR0 is set until either MMCR0 is reset or a performance
monitor interrupt is generated. Table 11-8 lists the selectable events and their encodings.
Table 11-8. PMC1 EventsMMCR0[19D25] Select Encodings
Number
Event
Description
0 (000_0000)
Nothing
Register counter holds current value
1 (000_0001)
Processor cycles
Counts every processor cycle
2 (000_0010)
Instructions completed Counts completed instructions. Does not include folded branches. 0, 1, or 2
instructions per cycle.
3 (000_0011)
TBL bit transitions
Count transitions from 0 to 1 of TBL bits speciTed through MMCR0[TBSEL]
4 (000_0100)
Instructions
dispatched
Counts dispatched instructions. 0, 1, or 2 instructions per cycle.
5 (000_0101)
eieio
instructions
completed
Counts
eieio
instructions completed
6 (000_0110)
ITLB table search
cycles
Counts cycles spent performing ITLB table search operations
7 (000_0111)
VPU instructions
completed
Counts instructions completed by the VPU (0, 1, or 2 instructions per cycle)
8 (000_1000)
VSIU wait
Counts cycles the AltiVec simple integer unit had a valid dispatch but invalid
operands
9 (000_1001)
Instruction breakpoint
matches
Counts the times that the address of an instruction being completed
matches the address in the IABR. Both the address in the IABR and the
completed instruction address are masked by BAMR. Some instruction
addresses (such as folded branches) never produce hits.
IABR_hit = [(IABR AND BAMR) == (EA AND BAMR)]
See Table 11-6 for more information on this event.
10 (000_1010)
Data breakpoint
matches
Data breakpoint matches. DABR hit = [(DABR[0D28] AND BAMR[0D28]) ==
(EA AND BAMR)]. See Table 11-6 for more information on this event.