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MPC7400 RISC Microprocessor Users Manual
Timing Considerations
clock cycle, giving enough time for the next pair of instructions to be fetched from the
instruction cache with no idle cycles. If instructions are not in the BTIC or the on-chip
instruction cache, they are fetched from the L2 cache or from system memory.
The MPC7400s instruction cache throttling feature, managed through the instruction
cache throttling control (ICTC) register, can lower the processors overall junction
temperature by slowing the instruction fetch rate. See Chapter 10, òPower and Thermal
Management.ó
Branch instructions are identiTed by the fetcher, and forwarded to the BPU directly,
bypassing the IQ. If the branch is unconditional or if the speciTed conditions are already
known, the branch can be resolved immediately. That is, the branch direction is known and
instruction fetching can continue from the correct location. Otherwise, the branch direction
must be predicted. The MPC7400 offers several resources to aid in quick resolution of
branch instructions and for improving the accuracy of branch predictions. These include the
following:
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Branch target instruction cacheThe 64-entry (four-way-associative) branch target
instruction cache (BTIC) holds branch target instructions so when a branch is
encountered in a repeated loop, usually the Trst two instructions in the target stream
can be fetched into the instruction queue on the next clock cycle. The BTIC can be
disabled and invalidated through bits in HID0.
Dynamic branch predictionThe 512-entry branch history table (BHT) is
implemented with two bits per entry for four degrees of predictionnot taken,
strongly not taken, taken, strongly taken. Whether a branch instruction is taken or
not taken can change the strength of the next prediction. This dynamic branch
prediction is not deTned by the PowerPC architecture.
To reduce aliasing, only predicted branches update the BHT entries. Dynamic
branch prediction is enabled by setting HID0[BHT]; otherwise, static branch
prediction is used.
Static branch predictionStatic branch prediction is deTned by the PowerPC
architecture and involves encoding the branch instructions. See Section 6.4.1.3.1,
òStatic Branch Prediction.ó
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Branch instructions that do not update the LR or CTR are removed from the instruction
stream either by branch folding or removal of fall-through branch instructions, as described
in Section 6.4.1.1, òBranch Folding and Removal of Fall-Through Branch Instructions.ó
Branch instructions that update the LR or CTR are treated as if they require dispatch (even
though they are not issued to an execution unit in the process). They are assigned a position
in the CQ to ensure that the CTR and LR are updated sequentially.
All other instructions are issued from the IQ0 and IQ1. The dispatch rate depends upon the
availability of resources such as the execution units, rename registers, and CQ entries, and
upon the serializing behavior of some instructions. Instructions are dispatched in program
order; an instruction in IQ1 cannot be dispatched ahead of one in IQ0.