
Chapter 2. Programming Model
2-23
The MPC7400 Processor Register Set
2.1.4 Instruction Cache Throttling Control Register (ICTC)
Reducing the rate of instruction fetching can control junction temperature without the
complexity and overhead of dynamic clock control. System software can control
instruction forwarding by writing a nonzero value to the ICTC register, a supervisor-level
register shown in Figure 2-11. The overall junction temperature reduction comes from the
dynamic power management of each functional unit when the MPC7400 is idle in between
instruction fetches. Phase-locked loop (PLL) and delay-locked loop (DLL) conTgurations
are unchanged.
Figure 2-11. Instruction Cache Throttling Control Register (ICTC)
Table 2-12 describes the bit Telds for the ICTC register.
Table 2-12. ICTC Field Descriptions
Instruction cache throttling is enabled by setting ICTC[E] and writing the instruction
forwarding interval into ICTC[FI]. Enabling, disabling, and changing the instruction
forwarding interval affect instruction forwarding immediately.
The ICTC register can be accessed with the
mtspr
and
mfspr
instructions using SPR 1019.
2.1.5 Thermal Management Registers (THRM1DTHRM3)
The on-chip thermal management assist unit provides the following functions:
¥
¥
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Compares the junction temperature against user programmed thresholds
Generates a thermal management interrupt if the temperature crosses the threshold
Provides a way for a successive approximation routine to estimate junction
temperature
Bits
Name
Description
0D22
Reserved.
23D30
FI
Instruction forwarding interval expressed in processor clocks.
0x00 0 clock cycle.
0x01 1 clock cycle
.
.
.
0xFF 255 clock cycles
31
E
Cache throttling enable
0 Disable instruction cache throttling.
1 Enable instruction cache throttling.
0
22 23
30 31
E
FI
Reserved
ê 0 0 0 0 êê0 0 0 0 êê0 0 0 0 êê0 0 0 0 êê0 0 0 0 êê0 0 0 êê